Datasheet

325
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
22.8.6 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x14
Reset: 0x00000000
Property: Write-Protected
z Bits 31:16 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 15:8 – EVDx: Event Detected Channel x Interrupt Enable
0: The Event Detected Channel x interrupt is disabled.
1: The Event Detected Channel x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event
Detected Channel x interrupt.
z Bits 7:0 – OVRx: Overrun Channel x Interrupt Enable
0: The Overrun Channel x interrupt is disabled.
1: The Overrun Channel x interrupt is enabled.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000