Datasheet

270
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z Bits 17:16 – READMODE: NVMCTRL Read Mode
z Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 9:8 – SLEEPPRM: Power Reduction Mode during Sleep
Indicates the power reduction mode during sleep.
Table 20-5. Table 1-7. Power Reduction Mode during Sleep
z Bit 7 – MANW: Manual Write
0: Writing to the last word in the page buffer will automatically initiate a write operation to the page addressed in
the Address (ADDR) register. This includes writes to memory and auxiliary rows.
1: Write commands must be issued through the Command bit group in the Control A register(CTRLA.CMD).
z Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 4:1 – RWS: NVM Read Wait States
These bits give the number of wait states for a read operation. Zero indicates zero wait states, one indicates one
wait state, etc., up to 15 wait states.
This register is initialized to 0 wait states. Software can change this value based on the NVM access time and sys-
tem frequency.
z Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
READMODE Name Description
0x0 NO_MISS_PENALTY
The NVM Controller (cache system) does not insert wait states on
a cache miss. Gives the best system performance.
0x1 LOW_POWER
Reduces power consumption of the cache system, but inserts a
wait state each time there is a cache miss. This mode may not be
relevant if CPU performance is required, as the application will be
stalled and may lead to increase run time.
0x2 DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same
amount of time, determined by the number of programmed flash
wait states. This mode can be used for real-time applications that
require deterministic execution timings.
0x3 Reserved
SLEEPPRM[1:0] Name Description
0x0 WAKEONACCESS
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode upon first access.
0x1 WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.
NVM block exits low-power mode when exiting sleep.
0x2 Reserved
0x3 DISABLED Auto power reduction disabled.