Datasheet

263
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Procedure for Manual Page Writes (MANW=1)
The row to be written must be erased before the write command is given.
z Write to the page buffer by addressing the NVM main address space directly
z Write the page buffer to memory: CMD=Write Page and CMDEX
z The READY bit in the INTFLAG register will be low while programming is in progress, and access through the AHB
will be stalled
Procedure for Automatic Page Writes (MANW=0)
The row to be written must be erased before the last write to the page buffer is performed.
Note that partially written pages must be written with a manual write.
z Write to the page buffer by addressing the NVM main address space directly.
z When the last location in the page buffer is written, the page is automatically written to NVM main address
space.
z INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled.
20.6.5.3 Page Buffer Clear
The page buffer is automatically cleared to all ones after a page write is performed. If a partial page has been written and
it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be used.
20.6.5.4 Erase Row
Before a page can be written, the row that contains the page must be erased. The Erase Row command can be used to
erase the desired row. Erasing the row sets all bits to one. If the row resides in a region that is locked, the erase will not
be performed and the Lock Error bit in the Status register (STATUS.LOCKE) will be set.
Procedure for Erase Row
z Write the address of the row to erase ADDR. Any address within the row can be used.
z Issue an Erase Row command.
20.6.5.5 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section “Region Lock Bits” on page 261.
20.6.5.6 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the set and clear power
reduction mode commands. When the NVM Controller and block are in power reduction mode, the Power Reduction
Mode bit in the Status register (STATUS.PRM) is set.
20.6.6 NVM User Configuration
The NVM user configuration resides in the auxiliary space. See “Physical Memory Map” on page 20 for calibration and
auxiliary space address mapping.
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is protected against
write.
Table 20-2. Boot Loader Size
BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes
7 None 0
6 2 512
5 4 1024
4 8 2048