Datasheet

243
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
19.6.4 Additional Features
The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the
dedicated NMI Control register (NMICTRL - refer to NMICTRL). To select the sense for NMI, write to the NMISENSE bit
group in the NMI Control register (NMICTRL.NMISENSE). NMI filtering is enabled by writing a one to the NMI Filter
Enable bit (NMICTRL.NMIFILTEN).
NMI detection is enabled only by the NMICTRL.NMISENSE value, and the EIC is not required to be enabled.
After reset, NMI is configured to no detection mode.
When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when
set.
19.6.5 Interrupts
The EIC has the following interrupt sources:
z External interrupt pins (EXTINTx). See “Basic Operation” on page 241
z Non-maskable interrupt pin (NMI). See “Additional Features” on page 243
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request
is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled or the EIC is reset. See the INTFLAG register for details
on how to clear interrupt flags. The EIC has one common interrupt request line for all the interrupt sources (except the
NMI interrupt request line). Refer to “Processor and Architecture” on page 24 for details. The user must read the
INTFLAG (or NMIFLAG) register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Processor and
Architecture” on page 24 for details.
19.6.6 Events
The EIC can generate the following output events:
z External event from pin (EXTINTx).
Writing a one to an Event Output Control register (EVCTRLEXTINTEO) enables the corresponding output event. Writing
a zero to this bit disables the corresponding output event. Refer to “EVSYS – Event System” on page 306 for details on
configuring the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGy register, the corresponding event is
generated, if enabled.
Table 19-2. Interrupt Latency
Detection Mode Latency (Worst Case)
Level without filter 3 CLK_EIC_APB periods
Level with filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods
Edge without filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods
Edge with filter 6 GCLK_EIC periods + 3 CLK_EIC_APB periods