Datasheet

187
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
17.8.2 Configuration
Name: CONFIG
Offset: 0x1
Reset: N/A - Loaded from NVM User Row at startup
Property: Write-Protected, Enable-Protected, Write-Synchronized
z Bits 7:4 – WINDOW[3:0]: Window Mode Time-Out Period
In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. The
closed window periods are defined in Table 17-3.
These bits are loaded from NVM User Row at startup. Refer to “Non-Volatile Memory (NVM) User Row Mapping”
on page 22 for more details.
z Bits 3:0 – PER[3:0]: Time-Out Period
These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode
operation, these bits define the open window period. The different typical time-out periods are found in Table 17-4.
These bits are loaded from NVM User Row at startup. Refer to “Non-Volatile Memory (NVM) User Row Mapping”
on page 22 for more details.
Bit76543210
WINDOW[3:0] PER[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
ResetXXXXXXXX
Table 17-3. Window Mode Time-Out Period
Value Description
0x0 8 clock cycles
0x1 16 clock cycles
0x2 32 clock cycles
0x3 64 clock cycles
0x4 128 clock cycles
0x5 256 clocks cycles
0x6 512 clocks cycles
0x7 1024 clock cycles
0x8 2048 clock cycles
0x9 4096 clock cycles
0xA 8192 clock cycles
0xB 16384 clock cycles
0xC-0xF Reserved