Datasheet

146
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
16.8.2 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: Write-Protected
z Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable
0: The BOD33 Synchronization Ready interrupt is disabled.
1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Synchronization Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33
Synchronization Ready interrupt.
z Bit 10 – BOD33DET: BOD33 Detection Interrupt Enable
0: The BOD33 Detection interrupt is disabled.
Bit3130292827 26 25 24
Access R R R R R R R R
Reset00000 0 0 0
Bit2322212019 18 17 16
Access R R R R R R R R
Reset00000 0 0 0
Bit15141312 11 10 9 8
B33SRDY BOD33DET BOD33RDY DFLLRCS
Access
RRRRR/W R/W R/W R/W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000 0 0 0