Datasheet

139
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 25 for details.
16.6.11 Synchronization
Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock
domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before
writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in
PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any
write to any of the DFLL48M control registers while DFLLRDY is zero will be ignored. An interrupt is generated on a zero-
to-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set.
In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by
writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If
DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the
synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus.
The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral
bus. As a consequence, the prescaler registers require synchronization when written or read. The synchronization
results in a delay from when the initialization of the write or read operation begins until the operation is complete.
The write-synchronization is triggered by a write to the BOD33 control register. The Synchronization Ready bit
(PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write-synchronization starts and set when the
write-synchronization is complete. When the write-synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to
do any of the following will cause the peripheral bus to stall until the synchronization is complete:
z Writing to the BOD33control register
z Reading the BOD33 control register that was written
The user can either poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupts to check when the
synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation
will be completed after the ongoing read/write operation is synchronized.