Datasheet

137
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the
enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the
corresponding BOD33 register bit groups.
16.6.8.1 3.3V Brown-Out Detector (BOD33)
The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out
threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate either
an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection status can be
read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register.
At startup or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to “Non-
Volatile Memory (NVM) User Row Mapping” on page 22 for more details.
16.6.8.2 Continuous Mode
When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the
BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage.
Continuous mode is the default mode for BOD33.
16.6.8.3 Sampling Mode
The sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The
BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next
sampling clock tick.
Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (F
clksampling
) is controlled by
the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register.
The prescaler signal (F
clkprescaler
) is a 1kHz clock, output from the32kHz Ultra Low Power Oscillator, OSCULP32K.
As the sampling mode clock is different from the APB clock domain, synchronization among the clocks is necessary.
Figure 16-2 shows a block diagram of the sampling mode. The BOD33Synchronization Ready bits (PCLKSR.B33SRDY)
in the Power and Clocks Status register show the synchronization ready status of the synchronizer. Writing attempts to
the BOD33 register are ignored while PCLKSR.B33SRDY is zero.
Figure 16-2. Sampling Mode Block diagram
The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the
prescaler value. To change the prescaler value for the BOD33 during sampling mode, the following steps need to be
taken:
1. Wait until the PCLKSR.B33SRDY bit is set.
F
clksampling
F
clkprescaler
2
PSEL 1+()
------------------------------
=
US
ER INTERFA
CE
R
E
G
I
S
TER
S
(
APB clock domain
)
P
RE
SC
ALE
R
(
clk_prescale
r
domain
)
S
YN
C
HR
O
NIZER
P
S
EL
C
EN
MO
DE
ENABL
E
C
LK_APB
C
LK_PRE
SC
ALER
C
LK
_
SAMPLIN
G