Datasheet

130
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
16.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
16.5.1 I/O Lines
I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration.
16.5.2 Power Management
The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes.
16.5.3 Clocks
The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller
(GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M and DFLL48M.
The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on
page 101.
The clock used by BOD33in sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB).
Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface
clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between
the clock domains. Refer to “Synchronization” on page 139 for further details.
16.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 25 for details.
16.5.5 Debug Operation
When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
If a debugger connection is detected by the system, BOD33 reset will be blocked.
16.5.6 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 28 for details.
16.5.7 Analog Connections
The 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal must be
connected between the XIN and XOUT pins, along with any required load capacitors. For details on recommended
oscillator characteristics and capacitor load, refer to the “Electrical Characteristics” on page 563 for details.