Datasheet

119
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
15.8.6 APBC Clock Select
Name: APBCSEL
Offset: 0x0B
Reset: 0x00
Property: Write-Protected
z Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 2:0 – APBCDIV[2:0]: APBC Prescaler Selection
These bits define the division ratio of the APBC clock prescaler (2
n
).
Bit76543210
APBCDIV[2:0]
Access R R R R R R/W R/W R/W
Reset00000000
Table 15-9. APBC Prescaler Selection
APBCDIV[1:0] Description
0x0 Divide by 1
0x1 Divide by 2
0x2 Divide by 4
0x3 Divide by 8
0x4 Divide by 16
0x5 Divide by 32
0x6 Divide by 64
0x7 Divide by 128