Datasheet

104
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
15.6 Functional Description
15.6.1 Principle of Operation
15.6.1.1 Synchronous Clocks
The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the
synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the
derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as f
CPU
≥ f
APBx
. The
synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for each
module in each synchronous clock domain can be individually masked to avoid power consumption in inactive modules.
Depending on the sleep mode, some clock domains can be turned off (see Table 15-4 on page 109).
15.6.1.2 Reset Controller
The Reset Controller collects the various reset sources and generates reset for the device. The device contains a power-
on-reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset
circuitry to guarantee stable operation when powering up the device.
15.6.1.3 Sleep Mode Controller
In ACTIVE mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep
Mode Controller allows the user to choose between different sleep modes depending on application requirements, to
save power (see Table 15-4 on page 109).
15.6.2 Basic Operation
15.6.2.1 Initialization
After a power-on reset, the PM is enabled and the Reset Cause (RCAUSE - refer to RCAUSE for details) register
indicates the POR source. The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU
starts running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is
in the ACTIVE mode.
By default, only the necessary clocks are enabled (see Table 15-1).
15.6.2.2 Enabling, Disabling and Resetting
The PM module is always enabled and can not be reset.
15.6.2.3 Selecting the Main Clock Source
Refer to “GCLK – Generic Clock Controller” on page 79 for details on how to configure the main clock source.
15.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the
synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by
writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock
frequency determined by this equation:
Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure
correct operation, frequencies must be selected so that f
CPU
≥ f
APBx
. Also, frequencies must never exceed the specified
maximum frequency for each clock domain.
Note that the AHB clock is always equal to the CPU clock.
f
CPU
f
main
2
CPUDIV
----------------------
=