Datasheet

103
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
15.5.3 Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the power manager, and the default state of
CLK_PM_APB can be found in Table 15-1. If this clock is disabled in the Power Manager, it can only be re-enabled by a
reset.
A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by
default in the Generic Clock Controller, and can be re-configured by the user if needed. Refer to “GCLK – Generic Clock
Controller” on page 79 for details.
15.5.3.1 Main Clock
The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit
prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.
15.5.3.2 CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.
15.5.3.3 AHB Clock
The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is always
synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned off. A clock
gate is inserted from the common AHB clock to any AHB clock of a peripheral.
15.5.3.4 APBx Clocks
The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx
clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU clock
is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx bus.
15.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 25 for details.
15.5.5 Events
Not applicable.
15.5.6 Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks generated from
the PM are kept running to allow the debugger accessing any modules. As a consequence, power measurements are not
possible in debug mode.
15.5.7 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
z Interrupt Flag register (INTFLAG). Refer to INTFLAG for details
z Reset Cause register (RCAUSE). Refer to RCAUSE for details
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 28 for details.
15.5.8 Analog Connections
Not applicable.