Atmel SAM D20J / SAM D20G / SAM D20E SMART ARM-Based Microcontroller DATASHEET Description The Atmel® | SMART™ SAM D20 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM D20 devices operate at a maximum frequency of 48MHz and reach 2.14 Coremark/MHz.
Features z Processor ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier Memories z 16/32/64/128/256KB in-system self-programmable flash z 2/4/8/16/32KB SRAM System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) z External Interrupt Controller (EIC) z 16 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface Low Power z
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Ordering Code FLASH (bytes) SRAM (bytes) Package ATSAMD20E17A-AU Carrier Type Tray TQFP32 ATSAMD20E17A-AUT Tape & Reel 128K 16K ATSAMD20E17A-MU Tray QFN32 ATSAMD20E17A-MUT Tape & Reel ATSAMD20E18A-AU Tray TQFP32 ATSAMD20E18A-AUT Tape & Reel 256K 32K ATSAMD20E18A-MU Tray QFN32 ATSAMD20E18A-MUT 2.
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Pinout 4.1 SAM D20J 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB03 PB02 PB01 PB00 PB31 PB30 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 PB23 PB22 4.
48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 PB23 PB22 SAM D20G 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 VDDIO GND PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 13 14 15 16 17 18 19 20 21 22 23 24 PA00 PA01 PA02 PA03 GNDANA VDDANA PB08 PB09 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 VDDIO GND PB10 PB11 PA12 PA13 PA14 PA15 4.
32 31 30 29 28 27 26 25 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 SAM D20E 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 9 10 11 12 13 14 15 16 PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 VDDANA GND PA08 PA09 PA10 PA11 PA14 PA15 4.
5. I/O Multiplexing and Considerations 5.1 Multiplexed Signals Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one.
Table 5-1.
2. 3. 4. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to the “I2C Pins” on page 572 for details on the I2C pin characteristics Note that TC6 and TC7 are not supported on the SAM D20G. Refer to “Configuration Summary” on page 3 for details. This function is only activated in the presence of a debugger 5.2 Other Functions 5.2.
6. Signal Descriptions List The following table gives details on signal names classified by peripheral.
Signal Name Function Type PA28 - PA27 Parallel I/O Controller I/O Port A I/O PA31 - PA30 Parallel I/O Controller I/O Port A I/O PB17 - PB00 Parallel I/O Controller I/O Port B I/O PB23 - PB22 Parallel I/O Controller I/O Port B I/O PB31 - PB30 Parallel I/O Controller I/O Port B I/O Active Level Atmel | SMART SAM D20 [DATASHEET] Atmel-42129K–SAM-D20_datasheet–06/2014 15
ADC PA[7:2] VDDIO VDDIN GND Power Domain Overview VDDCORE 7.1 GNDANA Power Supply and Start-Up Considerations VDDANA 7. VOLTAGE REGULATOR PB[31:10] OSC8M PA[13:8] BOD12 XOSC AC PB[9:0] PA[15:14] PA[31:16] DAC PTC Digital Logic (CPU, peripherals) PA[1:0] XOSC32K POR OSC32K OSCULP32K 7.2 Power Supply Considerations 7.2.1 Power Supplies DFLL48M BOD33 The Atmel® SAM D20 has several different power supply pins: z VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.62V to 3.63V.
For decoupling recommendations for the different power supplies, refer to the schematic checklist. Refer to “Schematic Checklist” on page 608 for details. 7.2.2 Voltage Regulator The voltage regulator has two different modes: 7.2.3 z Normal mode: To be used when the CPU and peripherals are running z Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode Typical Powering Schematics The SAM D20 uses a single supply from 1.62V to 3.63V.
7.3 Power-Up This section summarizes the power-up sequence of the SAM D20. The behavior after power-up is controlled by the Power Manager. Refer to “PM – Power Manager” on page 101 for details. 7.3.1 Starting of Clocks After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device. Once the power has stabilized, the device will use a 1MHz clock.
8. Product Mapping Figure 8-1.
9. Memories 9.1 Embedded Memories 9.2 z Internal high-speed flash z Internal high-speed RAM, single-cycle access at full speed z Dedicated flash area for EEPROM emulation Physical Memory Map The High-Speed bus is implemented as a Bus Matrix. Refer to “High-Speed Bus Matrix” on page 26 for details. All HighSpeed bus addresses are fixed, and they are never remapped. The 32-bit physical address space is mapped as follows: Table 9-1.
Figure 9-1.
9.3 Non-Volatile Memory (NVM) User Row Mapping The NVM User Row contains calibration data that are automatically read at device power on. The NVM User Row can be read at address 0x804000. To write the NVM User Row refer to “NVMCTRL – Non-Volatile Memory Controller” on page 258. Note that when writing to the User Row the values will only be loaded at device reset. Table 9-3.
9.4 NVM Software Calibration Area Mapping The NVM Software Calibration Area contains calibration data that are measured and written during production test. These calibration values should be read by the application software and written back to the corresponding register. The NVM Software Calibration Area can be read at address 0x806020. The NVM Software Calibration Area can not be written. Table 9-4. 9.
10. Processor and Architecture 10.1 Cortex-M0+ Processor The Atmel® SAM D20 implements the ARM® Cortex®-M0+ processor, which is based on the ARMv6 architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and upward compatible with the Cortex-M3 and Cortex-M4 processors. The ARM Cortex-M0+ implemented is revision r0p1. For more information, refer to www.arm.com. 10.1.
z Nested Vectored Interrupt Controller (NVIC) z z External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to “Nested Vector Interrupt Controller” on page 25 and the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Peripheral Source NVIC Line EIC NMI – External Interrupt Controller Non Maskable Interrupt 10.
10.3.
10.4 AHB-APB Bridge The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power APB domain. It is used to provide access to the programmable control registers of peripherals (see “Product Mapping” on page 19). to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See “PM – Power Manager” on page 101 for details. 10.5 PAC – Peripheral Access Controller 10.5.1 Overview There is one PAC associated with each AHB-APB bridge.
10.6 Register Description Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Refer to “Product Mapping” on page 19 for PAC locations. 10.6.
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Write Protect Set Name: WPSET Offset: 0x04 Reset: 0x00000002 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PORT NVMCTRL DSU Access R R R R R/W R/W R/W R Reset 0 0 0 0 0 0 1 0 z Bits 31:4 –
10.6.
Write Protect Set Name: WPSET Offset: 0x04 Reset: 0x00100000 Property: - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 PTC DAC AC ADC Access R R R R R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SERCOM5 SERCOM4 SERCOM3 SE
11. Peripherals Configuration Overview The following table shows an overview of all the peripherals in the device. The IRQ Line column shows the interrupt mapping, as described in “Nested Vector Interrupt Controller” on page 25. The AHB and APB clock indexes correspond to the bit in the AHBMASK and APBMASK (x = A, B or C) registers in the Power Manager, while the Enabled at Reset column shows whether the peripheral clock is enabled at reset (Y) or not (N).
Table 11-1.
12. DSU – Device Service Unit 12.1 Overview The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components in the system.
12.4 Signal Description Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. 12.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 12.5.
12.6 Debug Operation 12.6.1 Principle of Operation The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources: z CPU reset extension z Debugger probe detection For more details on the ARM debug components, refer to the ARM Debug Interface v5Architecture Specification. 12.6.2 CPU Reset Extension “CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released.
Figure 12-3. Hot-Plugging Detection Timing Diagram SWCLK RESET CPU_STATE reset running Hot-Plugging The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit (refer to “Security Bit” on page 264). This detection requires that pads are correctly powered.
tem continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 12.9 2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. Releasing RESET results in a debugger Cold-Plugging procedure. 4.
Figure 12-4. APB Memory Mapping 0x0000 DSU operating registers 0x00FC 0x0100 0x01FD Internal address range (cannot be accessed from debug tools when the device is protected by the NVMCTRL security bit) Replicated DSU operating registers Empty External address range (can be accessed from debug tools with some restrictions) 0x1000 DSU CoreSight ROM 0x1FFC Some features not activated by APB transactions are not available when the device is protected: Table 12-1.
Table 12-2. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size JEP-106 CC code 4 Atmel continuation code: 0x0 JEP-106 ID code 7 Atmel device ID: 0x1F 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 PARTNUM 12 Contains 0xCD0 to indicate that DSU is present 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants.
12.11.3 32-bit Cyclic Redundancy Check (CRC32) The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including flash and AHB RAM). When the CRC32 command is issued from: z The internal range, the CRC32 can be operated at any memory location z The external range, the CRC32 operation is restricted; DATA, ADDR and LENGTH values are forced (see below) Table 12-3.
read. The DCC0 and DCC1 registers are shared with the onboard memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. 12.11.5 Testing of Onboard Memories (MBIST) The DSU implements a feature for automatic testing of memory also known as MBIST. This is primarily intended for production test of onboard memories.
z ADDR: Address of the word containing the failing bit. z DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Table 12-4.
Table 12-6. Available Features When Operated From The External Address Range Features Chip-Erase command and status CRC32 Availability From The External Address Range Yes Yes, only full array or full EEPROM CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories (MBIST) Yes STATUSA.CRSTEXT clearing No (STATUSA.
12.12 Register Summary Table 12-7.
0x1000 7:0 0x1001 15:8 FMT EPRES FMT EPRES ADDOFF[3:0] ENTRY0 0x1002 23:16 ADDOFF[11:4] 0x1003 31:24 ADDOFF[19:12] 0x1004 7:0 0x1005 15:8 ADDOFF[3:0] ENTRY1 0x1006 23:16 ADDOFF[11:4] 0x1007 31:24 ADDOFF[19:12] 0x1008 7:0 END[7:0] 15:8 END[15:8] 0x100A 23:16 END[23:16] 0x100B 31:24 END[31:24] 0x1FCC 7:0 0x1009 END 0x1FCD SMEMP 15:8 MEMTYPE 0x1FCE 23:16 0x1FCF 31:24 0x1FD0 7:0 0x1FD1 FKBC[3:0] JEPCC[3:0] 15:8 PID4 0x1FD2 23:16 0x1FD3 31:24 0x1FD4 Reser
0x1FF0 7:0 0x1FF1 PREAMBLEB0[7:0] 15:8 CID0 0x1FF2 23:16 0x1FF3 31:24 0x1FF4 7:0 0x1FF5 CCLASS[3:0] PREAMBLE[3:0] 15:8 CID1 0x1FF6 23:16 0x1FF7 31:24 0x1FF8 7:0 0x1FF9 PREAMBLEB2[7:0] 15:8 CID2 0x1FFA 23:16 0x1FFB 31:24 0x1FFC 7:0 0x1FFD PREAMBLEB3[7:0] 15:8 CID3 0x1FFE 23:16 0x1FFF 31:24 Atmel | SMART SAM D20 [DATASHEET] Atmel-42129K–SAM-D20_datasheet–06/2014 50
12.13 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 38 for details.
12.13.1 Control Name: CTRL Offset: 0x0000 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 CE MBIST CRC 1 0 SWRST Access R R R W W W R W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 4 – CE: Chip Erase Writing a zero to this bit has no effect.
12.13.2 Status A Name: STATUSA Offset: 0x0001 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
12.13.3 Status B Name: STATUSB Offset: 0x0002 Reset: 0x1X Property: Write-Protected Bit 7 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R R R R Reset 0 0 0 1 0 0 X X z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
12.13.
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12.13.7 Debug Communication Channel n Name: DCCn Offset: 0x0010+n*0x4 [n=0..
12.13.
z Bits 7:0 – DEVSEL[7:0]: Device Selection DEVSEL is used to identify a device within a product family and product series. The value corresponds to the Flash memory density, pin count and device variant parts of the ordering code. Refer to Table 12-8. for details. Table 12-8.
12.13.9 CoreSight ROM Table Entry n Name: ENTRYn Offset: 0x1000+n*0x4 [n=0..
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13. Clock System This chapter only aims to summarize the clock distribution and terminology in the SAM D20 device. It will not explain every detail of its configuration. For in-depth documentation, see the referenced module chapters. 13.1 Clock Distribution Figure 13-1.
Figure 13-2. Example of SERCOM clock PM Main Clock Controller SYSCTRL DFLL48M 13.2 GCLK_SERCOM0_APB GCLK Generic Clock Generator 1 Generic Clock Multiplexer 13 GCLK_SERCOM0_CORE SERCOM 0 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, some peripheral accesses by the CPU needs to be synchronized between the different clock domains.
Figure 13-3. Synchronization Asynchronous Domain (generic clock) Synchronous Domain (CLK_APB) Sync Non Synced reg Peripheral bus INTFLAG Write-Synced reg SYNCBUSY STATUS READREQ Synchronizer Write-Synced reg R/W-Synced reg 13.3.2 Write-Synchronization The write-synchronization is triggered by a write to any generic clock core register. The Synchronization Busy bit in the Status register (STATUS.
13.3.3 Read-Synchronization Reading a read-synchronized core register will cause the peripheral bus to stall immediately until the readsynchronization is complete. The Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set when the read-synchronization starts and cleared when the read-synchronization is complete. Refer to “Synchronization Delay” on page 77 for details on the synchronization delay. Note that reading a read-synchronized core register while STATUS.
13.3.7 Software Reset Write-Synchronization Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset write-synchronization.
source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator.
14. GCLK – Generic Clock Controller 14.1 Overview Several peripherals may require specific clock frequencies to operate correctly. The Generic Clock Controller consists of number of generic clock generators and generic clock multiplexers that can provide a wide range of clock frequencies. The generic clock generators can be set to use different external and internal clock sources. The selected clock can be divided down in the generic clock generator.
Figure 14-2.
14.5.4 Interrupts Not applicable. 14.5.5 Events Not applicable. 14.5.6 Debug Operation Not applicable. 14.5.7 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
z The generic clock that will be configured must be written to the ID bit group (CLKCTRL.ID) z The generic clock generator used as the source of the generic clock must be written to the GEN bit group (CLKCTRL.GEN) Refer to CLKCTRL register for details. 14.6.2.2 Enabling, Disabling and Resetting The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST).
clock source B is not ready, the generic clock generator will continue running with clock source A. As soon as clock source B is ready, however, the generic clock generator will switch to it. During the switching, the generic clock generator holds clock requests to clock sources A and B and then releases the clock source A request when the switch is done. The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL clocks).
14.6.3.2 Disabling a Generic Clock A generic clock is disabled by writing a zero to CLKCTRL.CLKEN. The SYNCBUSY bit will be cleared when this writesynchronization is complete. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete. When the generic clock is disabled, the generic clock is clock gated. 14.6.3.3 Selecting a Clock Source for the Generic Clock When changing a generic clock source by writing to CLKCTRL.
14.6.4.2 Generic Clock Enable after Reset The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That means that the configuration of the generic clock generators and generic clocks after reset is device-dependent. Refer to Table 14-7 and Table 14-8 for details on GENCTRL reset. Refer to Table 14-11 and Table 14-12 for details on GENDIV reset. Refer to Table 14-3 and Table 14-4 for details on CLKCTRL reset. 14.6.5 Sleep Mode Operation 14.6.5.
14.7 Register Summary Offset Name Bit Pos.
14.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-protected property in each individual register description. Refer to “Register Access Protection” on page 81 for details.
14.8.1 Control Name: CTRL Offset: 0x0 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 – SWRST: Software Reset 0: There is no reset operation ongoing.
14.8.2 Status Name: STATUS Offset: 0x1 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
14.8.3 Generic Clock Control This register allows the user to configure one of the generic clocks, as specified in the CLKCTRL.ID bit group. To write to the CLKCTRL register, do a 16-bit write with all configurations and the ID. To read the CLKCTRL register, first do an 8-bit write to the CLKCTRL.ID bit group with the ID of the generic clock whose configuration is to be read, and then read the CLKCTRL register.
Table 14-1. Generic Clock Generator Value Description 0x0 Generic clock generator 0 0x1 Generic clock generator 1 0x2 Generic clock generator 2 0x3 Generic clock generator 3 0x4 Generic clock generator 4 0x5 Generic clock generator 5 0x6 Generic clock generator 6 0x7 Generic clock generator 7 0x8-0xF Reserved z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Table 14-2. Generic Clock Selection ID (Continued) 0x0F SERCOM2_CORE 0x10 SERCOM3_CORE 0x11 SERCOM4_CORE 0x12 SERCOM5_CORE 0x13 TC0,TC1 0x14 TC2,TC3 0x15 TC4,TC5 0x16 TC6,TC7 0x17 ADC 0x18 AC_DIG 0x19 AC_ANA 0x1A DAC 0x1B PTC 0x1C-0x3F Reserved A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
Table 14-4. CLKCTRL Reset Value after a User Reset Module Instance Reset Value after a User Reset CLKCTRL.GEN CLKCTRL.CLKEN CLKCTRL.
14.8.4 Generic Clock Generator Control This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group. To write to the GENCTRL register, do a 32-bit write with all configurations and the ID. To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock generator those configuration is to be read, and then read the GENCTRL register.
z Bit 20 – DIVSEL: Divide Selection This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding generic clock generator must be zero or one. 0: The generic clock generator equals the clock source divided by GENDIV.DIV. 1: The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).
Table 14-5. Source Select Value Name Description 0x00 XOSC XOSC oscillator output 0x01 GCLKIN Generator input pad 0x02 GCLKGEN1 Generic clock generator 1 output 0x03 OSCULP32K OSCULP32K oscillator output 0x04 OSC32K OSC32K oscillator output 0x05 XOSC32K XOSC32K oscillator output 0x06 OSC8M OSC8M oscillator output 0x07 DFLL48M DFLL48M output 0x08-0x1F Reserved Reserved for future use z Bits 7:4 – Reserved These bits are unused and reserved for future use.
Table 14-7. GENCTRL Reset Value after a Power Reset Generic Clock Generator ID Reset Value after a Power Reset Generator Clock Source 0x00 0x00010600 OSC8M 0x01 0x00000001 XOSC 0x02 0x00010302 OSCULP32K 0x03 0x00000003 XOSC 0x04 0x00000004 XOSC 0x05 0x00000005 XOSC 0x06 0x00000006 XOSC 0x07 0x00000007 XOSC After a user reset, the reset value of the GENCTRL register is as shown in Table 14-8. Table 14-8.
14.8.5 Generic Clock Generator Division This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group. To write to the GENDIV register, do a 32-bit write with all configurations and the ID. To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator whose configuration is to be read, and then read the GENDIV register.
Table 14-9. Division Factor Generator Division Factor Bits Generic clock generator 0 8 division factor bits - DIV[7:0] Generic clock generator 1 16 division factor bits - DIV[15:0] Generic clock generators 2 5 division factor bits - DIV[4:0] Generic clock generators 3 - 7 8 division factor bits - DIV[7:0] z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Table 14-11. GENDIV Reset value after a Power Reset Generic Clock Generator ID Reset Value after a Power Reset 0x00 0x00000000 0x01 0x00000001 0x02 0x00000002 0x03 0x00000003 0x04 0x00000004 0x05 0x00000005 0x06 0x00000006 0x07 0x00000007 After a user reset, the reset value of the GENDIV register is as shown in Table 14-12. Table 14-12.
15. PM – Power Manager 15.1 Overview The Power Manager (PM) controls the reset, clock generation and sleep modes of the microcontroller. Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx.
15.3 Block Diagram Figure 15-1. PM Block Diagram POWER MANAGER CLK_APB OSC8M GCLK SYNCHRONOUS CLOCK CONTROLLER CLK_AHB PERIPHERALS CLK_CPU SLEEP MODE CONTROLLER CPU BOD12 USER RESET BOD33 POWER RESET POR WDT RESET CONTROLLER CPU RESET RESET SOURCES 15.4 Signal Description Signal Name Type Description RESET Digital input External reset Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins.
15.5.3 Clocks The PM bus clock (CLK_PM_APB) can be enabled and disabled in the power manager, and the default state of CLK_PM_APB can be found in Table 15-1. If this clock is disabled in the Power Manager, it can only be re-enabled by a reset. A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by default in the Generic Clock Controller, and can be re-configured by the user if needed.
15.6 Functional Description 15.6.1 Principle of Operation 15.6.1.1 Synchronous Clocks The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU ≥ fAPBx.
CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance, while keeping the APBx frequency constant. Figure 15-2.
Table 15-1.
to indicate that the main clock comes from OSC8M. The GCLK_MAIN clock source can be selected again by writing a zero to the CTRL.BKUPCLK bit. Writing the bit does not fix the failure, however. Note 1: The detector does not monitor while the main clock is temporarily unavailable (startup time after a wake-up, etc.) or in sleep mode. The Clock Failure Detector must be disabled before entering standby mode.
Figure 15-3. Reset Controller RESET CONTROLLER BOD12 BOD33 POR RTC 32kHz clock sources WDT with ALWAYSON Generic Clock with WRTLOCK Debug Logic RESET WDT Others CPU RCAUSE RESET SOURCES 15.6.2.9 Sleep Mode Controller Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register (SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select the level of the sleep mode.
Table 15-4.
15.6.3 SleepWalking SleepWalking is the capability for a device to temporarily wakeup clocks for peripheral to perform a task without wakingup the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be waken-up by an interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode. In Atmel | SMART SAM D20 devices, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock sources.
15.7 Register Summary Offset Name Bit Pos.
Offset Name Bit Pos.
15.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
15.8.1 Control Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 BKUPCLK 2 1 0 CFDEN Access R R R R/W R R/W R R Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.2 Sleep Mode Name: SLEEP Offset: 0x01 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 IDLE[1:0] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.3 CPU Clock Select Name: CPUSEL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CPUDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.4 APBA Clock Select Name: APBASEL Offset: 0x09 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBADIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.5 APBB Clock Select Name: APBBSEL Offset: 0x0A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBBDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.6 APBC Clock Select Name: APBCSEL Offset: 0x0B Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 APBCDIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.
15.8.
15.8.
15.8.
15.8.11 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Name: INTENCLR Offset: 0x34 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CFD CKRDY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
15.8.12 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Name: INTENSET Offset: 0x35 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 CFD CKRDY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
15.8.13 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x36 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 CFD CKRDY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
15.8.14 Reset Cause Name: RCAUSE Offset: 0x38 Reset: Latest Reset Source Property: – Bit 7 6 5 4 SYST WDT EXT 3 2 1 0 BOD33 BOD12 POR Access R R R R R R R R Reset 0 X X X 0 X X X z Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
16. 16.1 SYSCTRL – System Controller Overview The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage regulator and voltage reference of the device. Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals. All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR - refer to PCLKSR).
16.3 Block Diagram Figure 16-1. SYSCTRL Block Diagram SYSCTRL XOSC XOSC32K OSCILLATORS CONTROL OSC32K OSCULP32K OSC8M DFLL48M POWER MONITOR CONTROL BOD33 VOLTAGE REFERENCE CONTROL VOLTAGE REFERENCE SYSTEM STATUS (PCLKSR register) INTERRUPTS GENERATOR 16.
16.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1 I/O Lines I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration. 16.5.2 Power Management The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL interrupts can be used to wake up the device from sleep modes.
16.6 Functional Description 16.6.1 Principle of Operation XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, BOD33, and VREF are configured via SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their calibration values updated. The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by the SYSCTRL.
16.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation The XOSC can operate in two different modes: z External clock, with an external clock signal connected to the XIN pin z Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators, as described in the “GCLK – Generic Clock Controller” on page 79.
The XOSC32K can be used as a source for generic clock generators, as described in the “GCLK – Generic Clock Controller” on page 79. At power-on reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO functions are overridden on both pins.
16.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factorycalibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K whenever the power requirements are prevalent over frequency stability and accuracy. The OSCULP32K can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock Controller” on page 79.
Closed-Loop Operation In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way: 1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0 (DFLL48M_Reference).
Drift Compensation If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M. If the DFLLVAL.FINE value overflows or underflows due to large drift in temperature and/or voltage, the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register will be set.
The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the corresponding BOD33 register bit groups. 16.6.8.1 3.3V Brown-Out Detector (BOD33) The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register.
2. Write the selected value to the BOD33.PSEL bit group. 16.6.8.4 Hysteresis The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33 Hysteresis bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level. 16.6.9 Voltage Reference System Operation The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt Controller” on page 25 for details. 16.6.11 Synchronization Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.
16.7 Register Summary SYSCTRL Register Summary Offset Name 0x00 Bit Pos.
SYSCTRL Register Summary (Continued) Offset Name 0x28 Bit Pos. 7:0 0x29 FINE[7:0] 15:8 COARSE[5:0] FINE[9:8] DFLLVAL 0x2A 23:16 DIFF[7:0] 0x2B 31:24 DIFF[15:8] 0x2C 7:0 MUL[7:0] 0x2D 15:8 MUL[15:8] 0x2E 23:16 FSTEP[7:0] 0x2F 31:24 DFLLMUL 0x30 DFLLSYNC 0x31 Reserved 0x32 Reserved 0x33 Reserved 7:0 0x34 7:0 0x35 15:8 CSTEP[5:0] FSTEP[9:8] READREQ RUNSTDBY ACTION[1:0] HYST PSEL[3:0] ENABLE CEN MODE BOD33 0x36 23:16 0x37 31:24 0x38 Reserved ... ...
16.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description.
16.8.1 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt. z Bit 9 – BOD33RDY: BOD33 Ready Interrupt Enable 0: The BOD33 Ready interrupt is disabled.
z Bit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable 0: The OSC8M Ready interrupt is disabled. 1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt. z Bit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable 0: The OSC32K Ready interrupt is disabled.
16.8.2 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt. z Bit 9 – BOD33RDY: BOD33 Ready Interrupt Enable 0: The BOD33 Ready interrupt is disabled.
z Bit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable 0: The OSC8M Ready interrupt is disabled. 1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt. z Bit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable 0: The OSC32K Ready interrupt is disabled.
16.8.
Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Detection interrupt flag. z Bit 9 – BOD33RDY: BOD33 Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the BOD33 Ready interrupt flag.
z Bit 2 – OSC32KRDY: OSC32K Ready This flag is cleared by writing a one to it. This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY) and will generate an interrupt request if INTENSET.OSC32KRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the OSC32K Ready interrupt flag. z Bit 1 – XOSC32KRDY: XOSC32K Ready This flag is cleared by writing a one to it.
16.8.
z Bit 7 – DFLLLCKC: DFLL Lock Coarse 0: No DFLL coarse lock detected. 1: DFLL coarse lock detected. z Bit 6 – DFLLLCKF: DFLL Lock Fine 0: No DFLL fine lock detected. 1: DFLL fine lock detected. z Bit 5 – DFLLOOB: DFLL Out Of Bounds 0: No DFLL Out Of Bounds detected. 1: DFLL Out Of Bounds detected. z Bit 4 – DFLLRDY: DFLL Ready 0: The Synchronization is ongoing. 1: The Synchronization is complete. This bit is cleared when the synchronization of registers between clock domains is complete.
16.8.
Table 16-3. Start-UpTime for External Multipurpose Crystal Oscillator 0x6 64 3 1953µs 0x7 128 3 3906µs 0x8 256 3 7813µs 0x9 512 3 15625µs 0xA 1024 3 31250µs 0xB 2048 3 62500µs 0xC 4096 3 125000µs 0xD 8192 3 250000µs 0xE 16384 3 500000µs 0xF 32768 3 1000000µs Notes: 1. 2. 3. Number of cycles for the start-up counter. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set.
0: The oscillator is always on, if enabled. 1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. z Bit 6 – RUNSTDBY: Run in Standby This bit controls how the XOSC behaves during standby sleep mode: 0: The oscillator is disabled in standby sleep mode. 1: The oscillator is not stopped in standby sleep mode. If XOSC.
16.8.6 32kHz External Crystal Oscillator (XOSC32K) Control Name: XOSC32K Offset: 0x14 Reset: 0x0080 Property: Write-Protected Bit 15 14 13 12 11 10 WRTLOCK 9 8 STARTUP[2:0] Access R R R R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY AAMPEN EN1K EN32K XTALEN ENABLE R/W R/W R/W R/W R/W R/W R/W R 1 0 0 0 0 0 0 0 Access Reset z Bits 15:13 – Reserved These bits are unused and reserved for future use.
Notes: z 1. 2. 3. Number of cycles for the start-up counter. Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles. Bit 7 – ONDEMAND: On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral.
16.8.
z Bit 11 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time These bits select start-up time for the oscillator according to Table 16-6. The OSCULP32K oscillator is used as input clock to the startup counter. Table 16-6.
z Bit 3 – EN1K: 1kHz Output Enable 0: The 1kHz output is disabled. 1: The 1kHz output is enabled. z Bit 2 – EN32K: 32kHz Output Enable 0: The 32kHz output is disabled. 1: The 32kHz output is enabled. z Bit 1 – ENABLE: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled. z Bit 0 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
16.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Name: OSCULP32K Offset: 0x1C Reset: 0xXX Property: Write-Protected Bit 7 6 5 4 3 WRTLOCK Access Reset z 2 1 0 CALIB[4:0] R/W R R R/W R/W R/W R/W R/W 0 0 0 X X X X X Bit 7 – WRTLOCK: Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. 0: The OSCULP32K configuration is not locked. 1: The OSCULP32K configuration is locked.
16.8.
z Bits 27:16 – CALIB[11:0]: Oscillator Calibration These bits control the oscillator calibration. The calibration field is split in two: CALIB[11:6] is for temperature calibration CALIB[5:0] is for overall process calibration These bits are loaded from Flash Calibration at startup. z Bits 15:10 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
z Bit 0 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
16.8.10 DFLL48M Control Name: DFLLCTRL Offset: 0x24 Reset: 0x0080 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 QLDIS CCDIS Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LLAW STABLE MODE ENABLE ONDEMAND Access Reset R/W R R R/W R/W R/W R/W R 1 0 0 0 0 0 0 0 z Bits 15:10 – Reserved These bits are unused and reserved for future use.
z Bit 4 – LLAW: Lose Lock After Wake 0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped. 1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped. z Bit 3 – STABLE: Stable DFLL Frequency 0: FINE calibration tracks changes in output frequency. 1: FINE calibration register value will be fixed after a fine lock. z Bit 2 – MODE: Operating Mode Selection 0: The DFLL operates in open-loop operation.
16.8.
16.8.
16.8.13 DFLL48M Synchronization Name: DFLLSYNC Offset: 0x30 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 READREQ Access W R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – READREQ: Read Request To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
16.8.14 3.
Table 16-9.
z Bits 4:3 – ACTION: BOD33 Action These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold, as shown in Table 16-10. These bits are loaded from Flash User Row at startup. Refer to “Non-Volatile Memory (NVM) User Row Mapping” on page 22 for more details. Table 16-10.
16.8.15 Voltage Regulator System (VREG) Control Name: VREG Offset: 0x3C Reset: 0x0X02 Property: Write protected Bit 15 14 13 12 11 10 9 8 FORCELDO Access R R R/W R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY Access R R/W R R R R R R Reset 0 0 0 0 0 0 1 0 z Bits 15:14 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
16.8.
1: Temperature sensor is enabled and routed to an ADC input channel. z Bit 0 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
17. WDT – Watchdog Timer 17.1 Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
17.4 Signal Description Not applicable. 17.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines Not applicable. 17.5.2 Power Management The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes.
17.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger.
Enable bit in the Control register (CTRL.WEN) must be written to one and the Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined. 17.6.2.2 Configurable Reset Values On a power-on reset, some registers will be loaded with initial values from the NVM User Row. Refer to “Non-Volatile Memory (NVM) User Row Mapping” on page 22 for more details. This encompasses the following bits and bit groups: z Enable bit in the Control register (CTRL.
Figure 17-2. Normal-Mode Operation System Reset WDT Count Timely WDT Clear PER[3:0]=1 WDT Timeout Early Warning Interrupt EWOFFSET[3:0]=0 5 10 15 20 25 30 TOWDT 35 t [ms] 17.6.2.5 Window Mode In window-mode operation, the WDT uses two different time-out periods, a closed window time-out period (TOWDTW) and the normal, or open, time-out period (TOWDT). The closed window time-out period defines a duration from 8ms to 16s where the WDT cannot be reset.
17.6.3 Additional Features 17.6.3.1 Always-On Mode The always-on mode is enabled by writing a one to the Always-On bit in the Control register (CTRL.ALWAYSON). When the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set.
In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. 17.6.5 Synchronization Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when accessed.
17.7 Register Summary Register summary Offset Name Bit Pos.
17.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 179 for details.
17.8.1 Control Name: CTRL Offset: 0x0 Reset: N/A - Loaded from NVM User Row at startup Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 7 6 5 4 3 ALWAYSON Access Reset z 2 1 WEN ENABLE 0 R/W1 R/W R/W R/W R/W R/W R/W R/W X 0 0 0 0 X X 0 Bit 7 – ALWAYSON: Always-On This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the WDT will remain enabled until a power-on reset is received.
17.8.2 Configuration Name: CONFIG Offset: 0x1 Reset: N/A - Loaded from NVM User Row at startup Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 7 6 5 4 3 2 WINDOW[3:0] Access Reset z 1 0 PER[3:0] R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Bits 7:4 – WINDOW[3:0]: Window Mode Time-Out Period In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. The closed window periods are defined in Table 17-3.
Table 17-4.
17.8.3 Early Warning Interrupt Control Name: EWCTRL Offset: 0x2 Reset: N/A - Loaded from NVM User Row at startup Property: Write-Protected, Enable-Protected Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Acces s R R R R R/W R/W R/W R/W Reset 0 0 0 0 X X X X z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
17.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x4 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use.
17.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x5 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use.
17.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x6 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 EW Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
17.8.7 Status Name: STATUS Offset: 0x7 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
17.8.8 Clear Name: CLEAR Offset: Offset: 0x8 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 z Bits 7:0 – CLEAR: Watchdog Clear Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing any other value will issue an immediate system reset.
18. 18.1 RTC – Real-Time Counter Overview The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake up or overflow wake up mechanisms. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value.
Figure 18-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) 0 GCLK_RTC 10-bit Prescaler CLK_RTC_CNT COUNT = 16 Overflow 16 Periodic Events PER = Compare n 16 COMPn Figure 18-3. RTC Block Diagram (Mode 2 — Clock/Calendar) 0 MATCHCLR GCLK_RTC 10-bit Prescaler CLK_RTC_CNT 32 Y/M/D H:M:S 32 Y/M/D H:M:S = MASKn Periodic Events 18.4 Overflow CLOCK Alarm n ALARMn Signal Description Not applicable. 18.
18.5.3 Clocks The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_RTC_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on page 101. A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic Clock Controller before using the RTC. Refer to “GCLK – Generic Clock Controller” on page 79 for details.
18.6 Functional Description 18.6.1 Principle of Operation The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. 18.6.2 Basic Operation 18.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRL.
18.6.3 Operating Modes The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The operating mode is selected by the Operating Mode bit group in the Control register (CTRL.MODE). 18.6.3.1 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control register (CTRL.MODE) are zero, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 18-1.
The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next 0-to-1 transition of CLK_RTC_CNT. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored.
This results in a resolution of 1.0006PPM. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will speed up the frequency, and a negative value will slow down the frequency. Digital correction also affects the generation of the periodic events from the prescaler.
18.6.9 Synchronization Due to the asynchronicity between CLK_RTC_APB and GCLK_RTC some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
18.7 Register Summary The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary is presented for each of the three modes. Table 18-1. Register Summary - Mode 0 Registers Offset Name 0x00 Bit Pos.
Table 18-2. Register Summary - Mode 1 Registers Offset Name 0x00 Bit Pos.
Table 18-3. Register Summary - Mode 2 Registers Offset Name 0x00 Bit Pos.
18.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 197 for details.
18.8.1 Control 18.8.1.1 Mode 0 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MATCHCLR Access Reset MODE[1:0] R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 – Reserved These bits are unused and reserved for future use.
z Bit 7 – MATCHCLR: Clear on Match This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled. 0: The counter is not cleared on a Compare/Alarm 0 match. 1: The counter is cleared on a Compare/Alarm 0 match. This bit is not synchronized. z Bits 6:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
18.8.1.2 Mode 1 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST MODE[1:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:12 – Reserved These bits are unused and reserved for future use.
z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 3:2 – MODE[1:0]: Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. Table 18-7.
18.8.1.3 Mode 2 Name: CTRL Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP ENABLE SWRST R/W R/W R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset MODE[1:0] z Bits 15:12 – Reserved These bits are unused and reserved for future use.
z Bit 7 – MATCHCLR: Clear on Match This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled. 0: The counter is not cleared on a Compare/Alarm 0 match. 1: The counter is cleared on a Compare/Alarm 0 match. This bit is not synchronized. z Bit 6 – CLKREP: Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled.
18.8.2 Read Request Name: READREQ Offset: 0x02 Reset: 0x0010 Property: – Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 15 – RREQ: Read Request Writing a zero to this bit has no effect. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
18.8.3 Event Control 18.8.3.
18.8.3.2 Mode 1 Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Write-Protected, Enable-Protected Bit 15 14 13 12 11 10 OVFEO Access 9 8 CMPEO1 CMPEO0 R/W R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bit 15 – OVFEO: Overflow Event Output Enable 0: Overflow event is disabled and will not be generated.
18.8.3.3 Mode 2 Name: EVCTRL Offset: 0x04 Reset: 0x0000 Property: Write-Protected, Enabled-Protected Bit 15 14 13 12 11 10 9 OVFEO Access 8 ALARMEO0 R/W R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset z Bit 15 – OVFEO: Overflow Event Output Enable 0: Overflow event is disabled and will not be generated.
18.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). 18.8.4.1 Mode 0 Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 CMP0 Bit 7 – OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled.
18.8.4.2 Mode 1 Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 – OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. Writing a zero to this bit has no effect.
18.8.4.3 Mode 2 Name: INTENCLR Offset: 0x06 Reset: 0x00 Property: Write-protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 – OVF: Overflow Interrupt Enable 0: The Overflow interrupt is disabled. 1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. Writing a zero to this bit has no effect.
18.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. 18.8.5.1 Mode 0 Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R 0 0 0 0 0 0 0 0 CMP0 Bit 7 – OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled.
18.8.5.2 Mode 1 Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 – OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled. 1: The overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt.
18.8.5.3 Mode 2 Name: INTENSET Offset: 0x07 Reset: 0x00 Property: Write-Protected Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 – OVF: Overflow Interrupt Enable 0: The overflow interrupt is disabled. 1: The overflow interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
18.8.6 Interrupt Flag Status and Clear 18.8.6.1 Mode 0 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 CMP0 Bit 7 – OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated ifINTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
18.8.6.2 Mode 1 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: - Bit Access Reset z 7 6 5 4 3 OVF SYNCRDY R/W R/W R R R 0 0 0 0 0 2 1 0 CMP1 CMP0 R R/W R/W 0 0 0 Bit 7 – OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated ifINTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
18.8.6.3 Mode 2 Name: INTFLAG Offset: 0x08 Reset: 0x00 Property: – Bit Access Reset z 7 6 5 4 3 2 1 0 OVF SYNCRDY R/W R/W R R R R R R/W 0 0 0 0 0 0 0 0 ALARM0 Bit 7 – OVF: Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
18.8.7 Status Name: STATUS Offset: 0x0A Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
18.8.8 Debug Control Name: DBGCTRL Offset: 0x0B Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 – DBGRUN: Run During Debug This bit is not reset by a software reset.
18.8.9 Frequency Correction Name: FREQCORR Offset: 0x0C Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 SIGN Access Reset 3 2 1 0 VALUE[6:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bit 7 – SIGN: Correction Sign 0: The correction value is positive, i.e., frequency will be increased. 1: The correction value is negative, i.e., frequency will be decreased.
18.8.10 Counter Value 18.8.10.
18.8.10.2 Mode 1 Name: COUNT Offset: 0x10 Reset: 0x0000 Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0]: Counter Value These bits define the value of the 16-bit RTC counter.
18.8.11 Clock Value 18.8.11.
z Bits 5:0 – SECOND[5:0]: Second 0– 59.
18.8.12 Counter Period 18.8.12.1 Mode 1 Name: PER Offset: 0x14 Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0]: Counter Period These bits define the value of the 16-bit RTC period.
18.8.13 Compare n Value 18.8.13.1 Mode 0 Name: COMPn Offset: 0x18 + n*0x4 [n=0..
18.8.13.2 Mode 1 Name: COMPn Offset: 0x18 + n*0x2 [n=0..5] Reset: 0x0000 Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – COMP[15:0]: Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value.
18.8.14 Alarm n Value 18.8.14.1 Mode 2 Name: ALARMn Offset: 0x18 + n*0x8 [n=0..
z Bits 5:0 – SECOND[5:0]: Second The alarm second. Seconds are matched only if MASKn.SEL is greater than 0.
18.8.15 Alarm n Mask 18.8.15.1 Mode 2 Name: MASKn Offset: 0x1C + n*0x8 [n=0..3] Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
19. EIC – External Interrupt Controller 19.1 Overview The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled.
19.4 Signal Description Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 19.5 Product Dependencies In order to use this EIC, other parts of the system must be configured correctly, as described below. 19.5.
19.5.6 Debug Operation When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 19.5.
When the interrupt has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition. Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC. Filtering is enabled if bit Filter Enable x in the Configuration y register (CONFIGy.FILTENx) is written to one.
Table 19-2. Interrupt Latency Detection Mode Latency (Worst Case) Level without filter 3 CLK_EIC_APB periods Level with filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods Edge without filter 4 GCLK_EIC periods + 3 CLK_EIC_APB periods Edge with filter 6 GCLK_EIC periods + 3 CLK_EIC_APB periods 19.6.4 Additional Features The non-maskable interrupt pin can also generate an interrupt on edge or level detection, but it is configured with the dedicated NMI Control register (NMICTRL - refer to NMICTRL).
19.6.7 Sleep Mode Operation In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) enables the wake-up from pin EXTINTx. Writing a zero to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx. Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended. Figure 19-3.
19.7 Register Summary Table 19-3. Register Summary Name Bit Pos.
19.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-protected property in each individual register description. Refer to “Register Access Protection” on page 241 for details.
19.8.1 Control Name: CTRL Offset: 0x00 Reset: 0x00 Property: Write-Protected,Write-Synchronized Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 – ENABLE: Enable 0: The EIC is disabled. 1: The EIC is enabled.
19.8.2 Status Name: STATUS Offset: 0x01 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
19.8.3 Non-Maskable Interrupt Control Name: NMICTRL Offset: 0x02 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 NMIFILTEN 1 0 NMISENSE[2:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
19.8.4 Non-Maskable Interrupt Flag Status and Clear Name: NMIFLAG Offset: 0x03 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 NMI Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
19.8.
19.8.6 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
19.8.7 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
19.8.
19.8.
19.8.10 Configuration n Name: CONFIGn Offset: 0x18+n*0x4 [n=0..
Table 19-5.
20. NVMCTRL – Non-Volatile Memory Controller 20.1 Overview Non-volatile memory (NVM) is a reprogrammable flash memory that retains program and data storage even with power off. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block, while the APB interface is used for commands and configuration. 20.
20.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 20.5.1 Power Management The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL’s interrupts can be used to wake up the device from sleep modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes.
20.6.2 Basic Operations 20.6.2.1 Initialization After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user configuration. 20.6.2.2 Enabling, Disabling and Resetting Not applicable. 20.6.3 Memory Organization Refer to “Physical Memory Map” on page 20 for memory sizes and addresses for each device.
Figure 20-4. EEPROM Emulation and Boot Loader Allocation NVM Base Address + NVM size EEPROM Emulation allocation NVM Base Address + NVM size - EEPROM size Program allocation NVM Base Address + BOOTPROT size BOOT allocation NVM Base Address 20.6.4 Region Lock Bits The NVM block is grouped into 16 equally sized regions. The region size is dependent on the flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while INTFLAG.READY is low will be ignored. Read the CTRLA register description for more details. The CTRLB register must be used to control the power reduction mode, read wait states and the write mode. 20.6.5.
Procedure for Manual Page Writes (MANW=1) The row to be written must be erased before the write command is given.
BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes 3 16 4096 2 32 8192 1 64 16384 0 128 32768 The EEPROM bits indicates the Flash size reserved for EEPROM emulation according to the Table 20-3. EEPROM resides in the upper rows of the NVM main address space and are writable, regardless of the region lock status. Table 20-3.
20.7 Offset Register Summary Name 0x00 Bit Pos.
20.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description.
20.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 CMDEX[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CMD[6:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:8 – CMDEX: Command Execution This bit group should be written with the key value 0xA5 to enable the command written to CMD to be executed.
Table 20-4. Command Bit Description (Continued) CMD[4:0] Group Configuration Description 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x07-0x3F - Reserved 0x40 LR Lock Region - Locks the region containing the address location in the ADDR register.
20.8.
z Bits 17:16 – READMODE: NVMCTRL Read Mode READMODE Name Description NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
20.8.
Table 20-6. Page Size z PSZ[2:0] Name Description 0x0 8 8 bytes 0x1 16 16 bytes 0x2 32 32 bytes 0x3 64 64 bytes 0x4 128 128 bytes 0x5 256 256 bytes 0x6 512 512 bytes 0x7 1024 1024 bytes Bits 15:0 – NVMP: NVM Pages Indicates the number of pages in the NVM main address space.
20.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
20.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x10 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
20.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x14 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 ERROR READY Access R R R R R R R/W R Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
20.8.7 Status Name: STATUS Offset: 0x18 Reset: 0x0X00 Property: – Bit 15 14 13 12 11 10 9 8 SB Access R R R R R R R R Reset 0 0 0 0 0 0 0 X Bit 7 6 5 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM Access R R R R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 z Bits 15:9 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
This bit can be cleared by writing a one to its bit location. z Bit 0 – PRM: Power Reduction Mode This bit indicates the current NVM power reduction state. The NVM block can be set in power reduction mode in two ways: through the command interface or automatically when entering sleep with SLEEPPRM set accordingly. PRM can be cleared in three ways: through AHB access to the NVM block, through the command interface (SPRM and CPRM) or when exiting sleep with SLEEPPRM set accordingly.
20.8.
20.8.9 Lock Section Name: LOCK Offset: 0x20 Reset: 0xXXXX Property: – Bit 15 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset X X X X X X X X Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset X X X X X X X X z Bits 15:0 – LOCK: Region Lock Bits In order to set or clear these bits, the CMD register must be used. 0: The corresponding lock region is locked. 1: The corresponding lock region is not locked.
21. PORT 21.1 Overview The Port (PORT) controls the I/O pins of the microcontroller. The I/O pins are organized in a series of groups, collectively referred to as a line bundle, and each group can have up to 32 pins that can be configured and controlled individually or as a group. Each pin may either be used for general-purpose I/O under direct application control or assigned to an embedded device peripheral.
21.3 Block Diagram Figure 21-1. PORT Block Diagram PORT Peripheral Mux Select Control Status Port Line Bundles IP Line Bundles PORTMUX and Pad Line Bundles I/O PADS Analog Pad Connections PERIPHERALS Digital Controls of Analog Blocks ANALOG BLOCKS 21.4 Signal Description Signal Name Type Description Pxy Digital I/O General-purpose I/O pin y Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral.
21.5.2 Power Management During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled. If the PORT peripheral is shut down, the latches contained in the pad will retain their current configuration, such as the output value and pull settings. However, the PORT configuration registers and input synchronizers will lose their contents, and these will not be restored when PORT is powered up again.
The CPU accesses the PORT module through the IOBUS when it performs read or write from address 0x60000000. The PORT register map is equivalent to the one described in the register description section. This bus is generally used for low latency. The Data Direction (DIR - refer to DIR) and Data Output Value (OUT - refer to OUT) registers can be read, written, set, cleared or toggled using this bus, and the Data Input Value (IN - refer to IN) registers can be read.
consumption. Input value can always be read, whether the pin is configured as input or output, except if digital input is disabled by writing a zero to the INEN bit in the Pin Configuration registers (PINCFGy). The PORT also allows peripheral functions to be connected to individual I/O pins by writing a one to the corresponding PMUXEN bit in the PINCFGy registers and by writing the chosen selection to the Peripheral Multiplexing registers (PMUXn - refer to PMUXn) for that pin.
desired input value can be read from the (y / 32) bit in register IN as soon as the INEN bit in the Pin Configuration register (PINCFGy) is written to one. Refer to “I/O Multiplexing and Considerations” on page 11 for details on pin configuration. By default, the input synchronizer is clocked only when an input read is requested, which will delay the read operation by two CLK_PORT cycles.
21.6.4.2 Input Configuration Figure 21-4. I/O Configuration - Standard Input PULLEN PULLEN INEN DIR 0 1 0 PULLEN INEN DIR 1 1 0 DIR OUT IN INEN Figure 21-5. I/O Configuration - Input with Pull PULLEN DIR OUT IN INEN Note that when pull is enabled, the pull value is defined by the OUTx value. 21.6.4.3 Totem-Pole Output When configured for totem-pole (push-pull) output, the pin is driven low or high according to the corresponding bit setting in the OUT register.
Figure 21-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN PULLEN INEN DIR 0 1 1 PULLEN INEN DIR 1 0 0 DIR OUT IN INEN Figure 21-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN 21.6.4.4 Digital Functionality Disabled Figure 21-9.
21.7 Register Summary The I/O pins are organized in groups with up to 32 pins. Group 0 consists of the PA pins, group 1 the PB pins, etc. Each group has its own set of registers. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, while the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80. Bit Offset Name Pos.
Bit Offset Name 0x28 Pos.
21.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 282 for details.
21.8.1 Data Direction Name: DIR Offset: 0x00+x*0x80 [x=0..
21.8.2 Data Direction Clear This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Name: DIRCLR Offset: 0x04+x*0x80 [x=0..
21.8.3 Data Direction Set This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Name: DIRSET Offset: 0x08+x*0x80 [x=0..
21.8.4 Data Direction Toggle This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Name: DIRTGL Offset: 0x0C+x*0x80 [x=0..
21.8.5 Data Output Value This register sets the data output drive value for the individual I/O pins in the PORT. Name: OUT Offset: 0x10+x*0x80 [x=0..
21.8.6 Data Output Value Clear This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers. Name: OUTCLR Offset: 0x14+x*0x80 [x=0..
21.8.7 Data Output Value Set This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers. Name: OUTSET Offset: 0x18+x*0x80 [x=0..
21.8.8 Data Output Value Toggle This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers. Name: OUTTGL Offset: 0x1C+x*0x80 [x=0..
21.8.9 Data Input Value Name: IN Offset: 0x20+x*0x80 [x=0..
21.8.10 Control Name: CTRL Offset: 0x24+x*0x80 [x=0..
21.8.11 Write Configuration This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing. In order to avoid the side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero. Name: WRCONFIG Offset: 0x28+x*0x80 [x=0..
Writing a one to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN and WRCONFIG.PINMASK values. This bit will always read as zero. z Bit 29 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
0: The configuration of the corresponding I/O pin in the half-word group will be left unchanged. 1: The configuration of the corresponding I/O pin in the half-word pin group will be updated. These bits will always read as zero.
21.8.12 Peripheral Multiplexing n There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The n denotes the number of the set of I/O lines, while the m denotes the number of the group. Name: PMUXn Offset: 0x30+n*0x1+x*0x80 [n=0..15] (x=0..
21.8.13 Pin Configuration y There are up to 32 Pin Configuration registers in each group, one for each I/O line. The y denotes the number of the I/O line, while the x denotes the number of the group. Name: PINCFGy Offset: 0x40+y*0x1+x*0x80 [n=0..31] (x=0..1) Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 DRVSTR 2 1 0 PULLEN INEN PMUXEN Access R R/W R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 – Reserved This bit is unused and reserved for future use.
22. EVSYS – Event System 22.1 Overview The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to emit and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each module. Peripherals that respond to events are called event users. Peripherals that emit events are called event generators.
22.3 Block Diagram Figure 22-1. Event System Block Diagram EVSYS USER MUX CHANNELS PERIPHERALS GENERATOR EVENTS PERIPHERALS USERS EVENTS CLOCK REQUESTS GCLK 22.4 Signal Description Not applicable. 22.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 22.5.1 I/O Lines Not applicable. 22.5.
22.5.3 Clocks The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_EVSYS_APB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 101. Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_x). These are used for detection and propagation of events for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS.
1.1. The user to connect the channel is written to the User bit group (USER.USER) 2. Configure the channel by performing a single 32-bit write to the Channel (CHANNEL) register with: The channel to be configured is written to the Channel Selection bit group (CHANNEL.CHANNEL) 2.1. The path to be used is written to the Path Selection bit group (CHANNEL.PATH) 2.2. The type of edge detection to use on the channel is written to the Edge Selection bit group (CHANNEL.EDGSEL) 2.3.
To configure a channel, the Channel register must be written in a single 32-bit write. It is possible to read out the configuration of a channel by first selecting the channel by writing to CHANNEL.CHANNEL using a, 8-bit write, and then performing a read of the CHANNEL register. Event Generators The event generator is selected by writing to the Event Generator bit group in the Channel register (CHANNEL.EVGEN). A full list of selectable generators can be found in the CHANNEL register description.
Synchronous Path The synchronous path should be used when the event generator and the event channel share the same generic clock. If they do not share the same clock, a logic change from the event generator to the event channel might not be detected in the channel, which means that the event will not be propagated to the event user. When using the synchronous path, the channel is capable of generating interrupts.
z Event Detected Channel x interrupt (INTFLAG) Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
22.7 Register Summary Offset Name Bit Pos.
22.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description.
22.8.2 Channel This register allows the user to configure the channel specified in the CHANNEL bit group. To write to this register, do a single 32-bit write of all the configuration and channel selection data. To read from this register, first do an 8-bit write to the CHANNEL.CHANNEL bit group specifying the channel configuration to be read, and then read the Channel register (CHANNEL).
Table 22-1.
Table 22-3.
Table 22-3.
Table 22-4.
22.8.3 User Multiplexer This register is used to configure a specified event user. To write to this register, do a single 16-bit write of all the configuration and event user selection data. To read from this register, first do an 8-bit write to the USER.USER bit group specifying the event user configuration to be read, and then read USER.
Table 22-6.
22.8.
22.8.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x Interrupt Enable bit, which disables the Overrun Channel x interrupt.
22.8.6 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Channel x Interrupt Enable bit, which enables the Overrun Channel x interrupt.
22.8.
Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Channel x interrupt flag.
23. SERCOM – Serial Communication Interface 23.1 Overview The serial communication interface (SERCOM) can be configured to support a number of modes; I2C, SPI and USART. Once configured and enabled, all SERCOM resources are dedicated to the selected mode. The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching functionality. It can be configured to use the internal generic clock or an external clock, making operation in all sleep modes possible. 23.
23.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 I/O Lines Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to “PORT” on page 280 for details. From Figure 23-1 one can see that the SERCOM has four internal pads, PAD[3:0]. The signals from I2C, SPI and USART are routed through these SERCOM pads via a multiplexer.
23.5.8 Register Access Protection All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the following registers: z Interrupt Flag Status and Clear register (INTFLAG) z Address register (ADDR) z Data register (DATA) Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled.
23.6.2 Basic Operation 23.6.2.1 Initialization The SERCOM must be configured to the desired mode by writing to the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to Figure 23-1 for details. Table 23-1. SERCOM Modes CTRLA.
Figure 23-3. Baud Rate Generator Selectable Internal Clk (GCLK) Baud Rate Generator 1 Ext Clk fref Base Period 0 /2 /1 CTRLA.MODE[0] /8 /2 /16 0 Tx Clk 1 1 CTRLA.MODE 0 1 Clock Recovery Rx Clk 0 Table 23-2 contains equations for calculating the baud rate (in bits per second) and for calculating the BAUD register value for each mode of operation. For asynchronous mode, the BAUD register value is 16 bits (0 to 65,535), while for synchronous mode, the BAUD register value is 8 bits (0 to 255).
Table 23-3 shows the BAUD register value versus baud frequency at a serial engine frequency of 48MHz. This assumes a D value of 8 bits and an S value of 2 bits (10 bits, including start and stop bits). Table 23-3. BAUD Register Value vs. Baud Frequency BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF) 0 – 406 160 3MHz 407 – 808 161 2.981MHz 809 – 1205 162 2.963MHz 65206 31775 15.11kHz 65207 31871 15.06kHz 65208 31969 15.01kHz ...
23.6.3 Additional Features 23.6.3.1 Address Match and Mask The SERCOM address match and mask feature is capable of matching one address with a mask, two unique addresses or a range of addresses, based on the mode selected. The match uses seven or eight bits, depending on the mode. Address With Mask An address written to the Address bits in the Address register (ADDR.ADDR) with a mask written to the Address Mask bits in the Address register (ADDR.ADDRMASK) will yield an address match.
23.6.5 Interrupts Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs.
24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter 24.1 Overview The universal synchronous and asynchronous receiver and transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). Refer to “SERCOM – Serial Communication Interface” on page 329 for details. The USART uses the SERCOM transmitter and receiver configured as shown in Figure 24-1.
24.3 Block Diagram Figure 24-1. USART Block Diagram BAUD Internal Clk (GCLK) TX DATA baud rate generator /1 - /2 - /16 tx shift register TxD rx shift register RxD XCK Signal name 24.4 status rx buffer STATUS RX DATA Signal Description Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 24.
The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit groups (refer to the Control A register description) will define the physical position of the USART signals in Table 24-1. 24.5.2 Power Management The USART can continue to operate in any sleep mode where the selected source clock is running. The USART interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes.
24.5.9 Analog Connections Not applicable. 24.6 Functional Description 24.6.
z Communication mode (asynchronous or synchronous) must be selected by writing to the Communication Mode bit in the Control A register (CTRLA.CMODE) z SERCOM pad to use for the receiver must be selected by writing to the Receive Data Pinout bit group in the Control A register (CTRLA.RXPO) z SERCOM pads to use for the transmitter and external clock must be selected by writing to the Transmit Data Pinout bit in the Control A register (CTRLA.
Figure 24-3. Clock Generation Internal C lk (G C LK ) B au d R ate G enerator 1 0 B ase Period /2 /1 C T R LA .M O D E [0] /8 /2 /16 0 Tx C lk 1 1 XCK C TR LA .C M O D E 0 1 R x C lk 0 Synchronous Clock Operation When synchronous mode is used, the CTRLA.MODE bit group controls whether the transmission clock (XCK line) is an input or output. The dependency between the clock edges and data sampling or data change is the same for internal and external clocks.
24.6.2.5 Data Transmission A data transmission is initiated by loading the DATA register with the data to be sent. The data in TxDATA is moved to the shift register when the shift register is empty and ready to send a new frame. When the shift register is loaded with data, one complete frame will be transmitted. The Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.
rate desired. In this case, the BAUD register value should be selected to give the lowest possible error. Refer to “Asynchronous Mode BAUD Value Selection” on page 333 for details. Recommended maximum receiver baud-rate errors for various character sizes are shown in the table below. Table 24-2. Asynchronous Receiver Error D (Data bits + Parity) RSLOW(%) RFAST(%) Max Total Error (%) Recommended Max Rx Error (%) 5 94.12 107.69 +5.88/-7.69 ±2.5 6 94.92 106.67 +5.08/-6.67 ±2.0 7 95.52 105.
24.6.3.3 Start-of-Frame Detection The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal 8MHz oscillator must be selected as the GCLK_SERCOMx_CORE source. When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the 8MHz Internal Oscillator start-up time.
z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled.
24.7 Offset Register Summary Name 0x00 Bit Pos.
24.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 339 for details.
z Bit 30 – DORD: Data Order This bit indicates the data order when a character is shifted out from the Data register. 0: MSB is transmitted first. 1: LSB is transmitted first. This bit is not synchronized. z Bit 29 – CPOL: Clock Polarity This bit indicates the relationship between data output change and data input sampling in synchronous mode. This bit is not synchronized. Table 24-3.
Table 24-5. Receive Data Pinout RXPO[1:0] Name Description 0x0 PAD[0] SERCOM PAD[0] is used for data reception 0x1 PAD[1] SERCOM PAD[1] is used for data reception 0x2 PAD[2] SERCOM PAD[2] is used for data reception 0x3 PAD[3] SERCOM PAD[3] is used for data reception z Bits 19:17 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
These bits must be written to 0x0 or 0x1 to select the USART serial communication interface of the SERCOM. 0x0: USART with external clock. 0x1: USART with internal clock. These bits are not synchronized. z Bit 1 – ENABLE: Enable 0: The peripheral is disabled or being disabled. 1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.
24.8.
1: The transmitter is enabled or will be enabled when the USART is enabled. Writing a zero to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Writing a one to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART is enabled, CTRLB.TXEN will be cleared, and STATUS.SYNCBUSY will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 – CHSIZE[2:0]: Character Size These bits select the number of bits in a character. These bits are not synchronized. Table 24-8.
24.8.3 Debug Control Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
24.8.4 Baud Name: BAUD Offset: 0x0A Reset: 0x0000 Property: Enable-Protected, Write-Protected Bit 15 14 13 12 11 10 9 8 BAUD[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD: Baud Value These bits control the clock generation, as described in the SERCOM Baud Rate section.
24.8.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RXS RXC TXC DRE Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use.
24.8.6 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RXS RXC TXC DRE Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use.
24.8.7 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: Bit 7 6 5 4 3 2 1 0 RXS RXC TXC DRE Access R R R R R/W R R/W R Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 – RXS: Receive Start This flag is cleared by writing a one to it.
24.8.8 Status Name: STATUS Offset: 0x10 Reset: 0x0000 Property: Bit 15 14 13 12 11 10 9 8 R/W R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUFOVF FERR PERR SYNCBUSY Access Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete.
24.8.9 Data Name: DATA Offset: 0x18 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 DATA[8] Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:9 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
25. SERCOM SPI – SERCOM Serial Peripheral Interface 25.1 Overview The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). Refer to “SERCOM – Serial Communication Interface” on page 329 for details. The SPI uses the SERCOM transmitter and receiver configured as shown in “Full-Duplex SPI Master Slave Interconnection” on page 362.
25.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 25.5.1 I/O Lines Using the SERCOM’s I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to “PORT” on page 280 for details. When the SERCOM is configured for SPI operation, the pins should be configured according to Table 25-1. If the receiver is disabled, the data input pin can be used for other purposes.
25.5.7 Debug Operation When the CPU is halted in debug mode, the SPI continues normal operation. If the SPI is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The SPI can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL) register for details. 25.5.
25.6.2 Basic Operation 25.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRLA.ENABLE is zero): z Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) z Control B register (CTRLB), except Receiver Enable (RXEN) z Baud register (BAUD) z Address register (ADDR) Any writes to these registers when the SPI is enabled or is being enabled (CTRL.ENABLE is one) will be discarded.
(CTRLA.CPHA). SCK polarity is selected by the Clock Polarity bit in the Control A register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for the data signals to stabilize. Table 25-2.
25.6.2.6 Transferring Data Master When configured as a master (CTRLA.MODE is 0x3), the _SS line can be located at any general purpose I/O pin, and must be configured as an output. When the SPI is ready for a data transaction, software must pull the _SS line low. When writing a character to the Data register (DATA), the character will be transferred to the shift register when the shift register is empty.
25.6.3 Additional Features 25.6.3.1 Address Recognition When the SPI is configured for slave operation (CTRLA.MODE is 0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.
Figure 25-5. Multiple Slaves in Parallel shift register SPI Master MOSI MISO SCK _SS[0] MOSI MISO SCK _SS shift register _SS[n-1] MOSI MISO SCK _SS shift register SPI Slave 0 SPI Slave n-1 An alternate configuration is shown in Figure 25-6. In this configuration, all n attached slaves are connected in series. A common _SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a complete transaction. Figure 25-6.
The SPI has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt Controller” on page 25 for details. For details on clearing interrupt flags, refer to INTFLAG. 25.6.5 Events Not applicable. 25.6.
25.7 Offset Register Summary Name 0x00 Bit Pos.
25.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 364 for details.
25.8.
0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge. 1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge. This bit is not synchronized. Table 25-3.
z Bit 17:16 – DOPO: Data Out Pinout This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation, the slave select line (_SS) is controlled by DOPO, while in master operation the _SS line is controlled by the port configuration. In master operation, DO is MOSI. In slave operation, DO is MISO. These bits are not synchronized. Table 25-6.
1: The peripheral is enabled or being enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY is cleared when the operation is complete. This bit is not enable-protected. z Bit 0 – SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing.
25.8.
z Bit 16 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 15:14 – AMODE: Address Mode These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in master mode. Table 25-8.
25.8.3 Debug Control Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
25.8.4 Baud Rate Name: BAUD Offset: 0x0A Reset: 0x00 Property: Write-Protected, Enable-Protected Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – BAUD: Baud Register These bits control the clock generation, as described in the SERCOM “Clock Generation – Baud-Rate Generator” on page 332.
25.8.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RXC TXC DRE Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
25.8.6 Interrupt Enable Set This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 RXC TXC DRE Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
25.8.7 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 RXC TXC DRE Access R R R R R R R/W R Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
25.8.8 Status Name: STATUS Offset: 0x10 Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BUFOVF Access R R R R R R/W R R Reset 0 0 0 0 0 0 0 0 z Bit 15 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete.
25.8.
25.8.10 Data Name: DATA Offset: 0x18 Reset: 0x0000 Property: – Bit 15 14 13 12 11 10 9 8 DATA[8] Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:9 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
26. SERCOM I2C – SERCOM Inter-Integrated Circuit 26.1 Overview The inter-integrated circuit (I2C) interface is one of the available modes in the serial communication interface (SERCOM). Refer to “SERCOM – Serial Communication Interface” on page 329 for details. The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 26-1. Fields shown in capital letters are registers accessible by the CPU, while lowercase fields are internal to the SERCOM.
26.4 Signal Description Signal Name Type Description PAD[0] Digital I/O SDA PAD[1] Digital I/O SCL PAD[2] Digital I/O SDA_OUT (4-wire) PAD[3] Digital I/O SDC_OUT (4-wire) Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Note that not all the pins are I2C pins. Refer to Table 5-1 for details on the pin type for each pin. 26.
26.5.7 Debug Operation When the CPU is halted in debug mode, the I2C interface continues normal operation. If the I2C interface is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. The I2C interface can be forced to halt operation during debugging. Refer to the DBGCTRL register for details. 26.5.
Figure 26-2. Basic I2C Transaction Diagram SDA SCL 6 ... 0 S ADDRESS S 7 ... 0 R/W ADDRESS ACK R/W A 7 ... 0 DATA ACK DATA A DATA P ACK/NACK DATA A/A P Direction Address Packet Data Packet #0 Data Packet #1 Transaction Figure 26-3.
Any writes to these bits or registers when the I2C interface is enabled or is being enabled (CTRLA.ENABLE is one) will be discarded. Writes to these registers while the I2C interface is being disabled will be completed after the disabling is complete. Enable-protection is denoted by the Enable-Protection property in the register description.
Figure 26-4. Bus State Diagram RESET UNKNOWN (0b00) P + Timeout Sr S IDLE (0b01) BUSY (0b11) P + Timeout Command P Write ADDR (S) Arbitration Lost OWNER (0b10) Write ADDR(Sr) The bus state machine is active when the I2C master is enabled. After the I2C master has been enabled, the bus state is unknown. From the unknown state, the bus state machine can be forced to enter the idle state by writing to STATUS.BUSSTATE accordingly.
Figure 26-5. SCL Timing TRISE P TLOW S Sr SCL THIGH TBUF TFALL SDA THD;STA TSU;STO TSU;STA The following parameters are timed using the SCL low time period. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW) when non-zero, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) when BAUD.BAUDLOW is zero.
When BAUDLOW is non-zero, the following formula can be used to determine the SCL frequency: f SCL = f GCLK 10 + BAUD + BAUDLOW + f GCLK TRISE The following formulas can be used to determine the SCL TLOW and THIGH times: = T low T HIGH BAUD.BAUDLOW + 5 f GCLK = BAUD.BAUD + 5 f GCLK 26.6.2.5 I2C Master Operation The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most events.
Figure 26-6.
The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping and, therefore, not able to respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address packet by using a repeated start condition. However, the reason for the missing acknowledge can be that an invalid I2C slave address has been used or that the I2C slave is for some reason disconnected or faulty.
writing a 1 to the Smart Mode Enable bit in the Control A register (CTRLA.SMEN), are included to reduce software’s complexity and code size. The I2C slave operates according to the behavior diagram shown in Figure 26-7. The circles with a capital S followed by a number (S1, S2... etc.) indicate which node in the figure the bus logic can jump to based on software or hardware interaction. This diagram is used as reference for the description of the I2C slave operation throughout the document. Figure 26-7.
indicating data are needed for transmit. If not acknowledge is sent, the I2C slave will wait for a new start condition and address match. Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I2C slave command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on the STATUS.DIR bit. Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.
Figure 26-8. I2C Pad Interface SCL_OUT/ SDA_OUT SCL_OUT/ SDA_OUT pad PINOUT I2C Driver SCL/SDA pad SCL_IN/ SDA_IN PINOUT 26.6.3.4 Quick Command Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR. 26.6.
26.6.6 Synchronization Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be synchronized when accessed. A register can require: z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
26.7 Register Summary Table 26-1. Register Summary – Slave Mode Offset Name Bit Pos. 0x00 7:0 0x01 15:8 RUNSTDBY MODE[2:0]=100 ENABLE SWRST CTRLA 0x02 23:16 0x03 31:24 0x04 7:0 0x05 15:8 SDAHOLD[1:0] PINOUT LOWTOUT AMODE[1:0] SMEN CTRLB 0x06 23:16 0x07 31:24 ACKACT CMD[1:0] 0x08 Reserved ...
Table 26-1. Register Summary – Slave Mode (Continued) Offset Name 0x10 Bit Pos.
Table 26-2.
Table 26-2.
26.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to“Register Access Protection” on page 389 for details.
26.8.1 I2C Slave Register Description 26.8.1.
Table 26-3. SDA Hold Time Value Name Description 0x0 DIS Disabled 0x1 75 50-100ns hold time 0x2 450 300-600ns hold time 0x3 600 400-800ns hold time These bits are not synchronized. z Bits 19:17 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete. This bit is not enable-protected.
26.8.1.
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 26-4.
z Bits 7:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
26.8.1.3 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DRDY AMATCH PREC Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
26.8.1.4 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DRDY AMATCH PREC Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
26.8.1.5 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 DRDY AMATCH PREC Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
26.8.1.6 Status Name: STATUS Offset: 0x10 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 – SYNCBUSY: Synchronization Busy This bit is set when the synchronization of registers between clock domains is started.
z Bit 3 – DIR: Read / Write Direction The Read/Write Direction (STATUS.DIR) bit stores the direction of the last address packet received from a master. 0: Master write operation is in progress. 1: Master read operation is in progress. z Bit 2 – RXNACK: Received Not Acknowledge This bit indicates whether the last data packet sent was acknowledged or not. 0: Master responded with ACK. 1: Master responded with NACK.
26.8.1.
When the address match logic detects a match, INTFLAG.AMATCH is set and STATUS.DIR is updated to indicate whether it is a read or a write transaction. z Bit 0 – GENCEN: General Call Address Enable Writing a one to GENCEN enables general call address recognition. A general call address is an address of all zeroes with the direction bit written to zero (master write). 0: General call address recognition disabled. 1: General call address recognition enabled.
26.8.1.8 Data Name: DATA Offset: 0x18 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:8 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
26.8.2 I2C Master Register Description 26.8.2.
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up. Table 26-6. Inactive Timout Value Name Description 0x0 DIS Disabled 0x1 55US 5-6 SCL cycle time-out (50-60µs) 0x2 105US 10-11 SCL cycle time-out (100-110µs) 0x3 205US 20-21 SCL cycle time-out (200-210µs) Calculated time-out periods are based on a 100kHz baud rate. These bits are not synchronized. z Bits 27:22 – Reserved These bits are unused and reserved for future use.
z Bits 6:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 4:2 – MODE[2:0]: Operating Mode These bits must be written to 0x5 to select the I2C master serial communication interface of the SERCOM. These bits are not synchronized. z Bit 1 – ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled.
26.8.2.
Commands can only be issued when the Slave on Bus interrupt flag (INTFLAG.SB) or Master on Bus interrupt flag (INTFLAG.MB) is one. If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address. Issuing a command will set STATUS.SYNCBUSY. Table 26-8.
26.8.2.3 Debug Control Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGSTOP Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
26.8.2.
26.8.2.5 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SB MB Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
26.8.2.6 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SB MB Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use.
26.8.2.7 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 SB MB Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
26.8.2.8 Status Name: STATUS Offset: 0x10 Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CLKHOLD LOWTOUT RXNACK ARBLOST BUSERR Access R R/W R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z BUSSTATE[1:0] Bit 15 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete.
Table 26-9. Bus State Value Name 0x0 Unknown 0x1 Idle 0x2 Owner 0x3 Busy Description The bus state is unknown to the I2C master and will wait for a stop condition to be detected or wait to be forced into an idle state by software The bus state is waiting for a transaction to be initialized The I2C master is the current owner of the bus Some other I2C master owns the bus When the master is disabled, the bus-state is unknown.
26.8.2.9 Address Name: ADDR Offset: 0x14 Reset: 0x0000 Property: Write-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:8 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
26.8.2.10 Data Name: DATA Offset: 0x18 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:8 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
27. TC – Timer/Counter 27.1 Overview The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM). 27.
Block Diagram Figure 27-1. Timer/Counter Block Diagram BASE COUNTER PER PRESCALER count COUNTER OVF/UNF (INT Req.) clear load COUNT CONTROL LOGIC direction ERR (INT Req.) =0 Zero Update Top = event 27.3 Compare / Capture CONTROL LOGIC WOx Out WAVEFORM GENERATION CC0 match = MCx (INT Req.
27.4 Signal Description Signal Name Type Description WO[1:0] Digital output Waveform output Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 27.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines Using the TC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 280 for details.
z Read Request register (READREQ) z Count register (COUNT), “Counter Value” on page 467 z Period register (PER), “ Period Value” on page 470 z Compare/Capture Value registers (CCx), “ Compare/Capture” on page 471 Write-protection is denoted by the Write-Protection property in the register description. When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply for accesses through an external debugger.
z If the GCLK_TCx frequency used should be prescaled, this can be selected in the Prescaler bit group in the Control A register (CTRLA.PRESCALER) z If the prescaler is used, one of the presync modes must be chosen in the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC) z One-shot mode can be selected by writing a one to the One-Shot bit in the Control B Set register (CTRLBSET.
z COUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can be used as the top value for waveform generation. z COUNT16: This is the default counter mode. There is no dedicated period register in this mode. z COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. This pairing is explained in “Clocks” on page 436. The even-numbered TC instance will act as master to the odd-numbered TC peripheral, which will act as a slave.
When a retrigger is evoked with the counter stopped, the counter will continue counting from the value in the COUNT register. Note: When retrigger event action is configured and enabled as an event action, enabling the counter will not start the counter. The counter will start at the next incoming event and restart on any following event.
Figure 27-4. Normal Frequency Operation CNT written "wraparound " TOP COUNT CCx Zero WO[x] When MFRQ is used, the value in CC0 will be used as the top value and WO[0] will toggle on every overflow/underflow. Figure 27-5. Match Frequency Operation Period (T) Direction Change COUNT written " wraparound " COUNT TOP Zero WO[0] PWM Operation In PWM operation, the CCx registers control the duty cycle of the waveform generator output.
Figure 27-6. Normal PWM Operation Period(T) CCn= BOT CCn= TOP "wraparound " "match " TOP COUNT CC n Zero WO[x] In match operation, Compare/Capture register CC0 is used as the top value, in this case a negative pulse will appear on WO[0] on every overflow/underflow.
When counting up a change from a top value that is lower relative to the old top value can make the counter miss this change if the counter value is larger than the new top value when the change occurred. This will make the counter count to the max value. An example of this can be seen in Figure 27-8. Figure 27-8.
Period and Pulse-Width Capture Action The TC can perform two input captures and restart the counter on one of the edges. This enables the TC to measure the pulse width and period. This can be used to characterize the frequency and duty cycle of an input signal: 1 f = --T tp --dutyCycle = T When using PPW event action, the period (T) will be captured into CC0 and the pulse width (tp) in CC1. In PWP event action, the pulse width (tp) will be captured in CC0 and the period (T) in CC1.
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the TC is reset. See the INTFLAG register for details on how to clear interrupt flags.
Write-synchronization is denoted by the Write-Synchronized property in the register description. The following registers need synchronization when written: z Control B Clear register (CTRLBCLR) z Control B Set register (CTRLBSET) z Control C register (CTRLC) z Count Value register (COUNT) z Period Value register (PERIOD) z Compare/Capture Value registers (CCx) Write-synchronization is denoted by the Write-Synchronized property in the register description.
27.7 Register Summary Table 27-1. Register Summary – 8-Bit Mode Registers Offset Name 0x00 Bit Pos.
Table 27-2. Register Summary – 16-Bit Mode Registers Offset Name 0x00 Bit Pos.
Table 27-3. Register Summary – 32-Bit Mode Registers Offset Name 0x00 Bit Pos.
27.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description.
27.8.1 Control A Name: CTRLA Offset: 0x00 Reset: 0x0000 Property: Write-Protected, Enable-Protected, Write-Synchronized Bit 15 14 13 12 PRESCSYNC[1:0] 11 10 RUNSTDBY 9 8 PRESCALER[2:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ENABLE SWRST WAVEGEN[1:0] MODE[1:0] Access R R/W R/W R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:14 – Reserved These bits are unused and reserved for future use.
Table 27-5. Prescaler Value Name Description 0x0 DIV1 Prescaler: GCLK_TC 0x1 DIV2 Prescaler: GCLK_TC/2 0x2 DIV4 Prescaler: GCLK_TC/4 0x3 DIV8 Prescaler: GCLK_TC/8 0x4 DIV16 Prescaler: GCLK_TC/16 0x5 DIV64 Prescaler: GCLK_TC/64 0x6 DIV256 Prescaler: GCLK_TC/256 0x7 DIV1024 Prescaler: GCLK_TC/1024 z Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Table 27-7. TC Mode Value Name Description 0x0 COUNT16 Counter in 16-bit mode 0x1 COUNT8 Counter in 8-bit mode 0x2 COUNT32 Counter in 32-bit mode 0x3 - Reserved z Bit 1 – ENABLE: Enable 0: The peripheral is disabled. 1: The peripheral is enabled. Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.
27.8.2 Read Request For a detailed description of this register and its use, refer to the“Synchronization” on page 445. Name: READREQ Offset: 0x02 Reset: 0x0000 Property: - Bit 15 14 13 12 11 10 9 8 RREQ RCONT Access W R/W R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 15 – RREQ: Read Request Writing a zero to this bit has no effect.
27.8.3 Control B Clear This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect. Writing a one to this bit will make the counter count up.
27.8.4 Control B Set This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBCLR) register.
1: The timer/counter is counting down (decrementing). Writing a zero to this bit has no effect Writing a one to this bit will make the counter count down.
27.8.5 Control C Name: CTRLC Offset: 0x06 Reset: 0x00 Property: Write-Protected, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 CPTEN1 CPTEN0 3 2 1 0 INVEN1 INVEN0 Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
27.8.6 Debug Control Name: DBGCTRL Offset: 0x08 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
27.8.7 Event Control Name: EVCTRL Offset: 0x0A Reset: 0x0000 Property: Write-Protected, Enable-Protected Bit 15 14 13 12 MCEO1 MCEO0 11 10 9 8 OVFEO Access R R R/W R/W R R R R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCEI TCINV EVACT[2:0] Access R R R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:14 – Reserved These bits are unused and reserved for future use.
z Bit 4 – TCINV: TC Inverted Event Input This bit inverts the input event source when used in PWP or PPW measurement. 0: Input event source is not inverted. 1: Input event source is inverted. This bit is not enable-protected. z Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
27.8.8 Interrupt Enable Clear This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x0C Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 MC1 MC0 SYNCRDY 2 1 0 ERR OVF Access R R/W R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use.
27.8.9 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x0D Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 MC1 MC0 SYNCRDY 2 1 0 ERR OVF Access R R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use.
27.8.10 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x0E Reset: 0x00 Property: - Bit 7 6 5 4 3 2 MC1 MC0 SYNCRDY 1 0 ERR OVF Access R R R/W R/W R/W R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
27.8.11 Status Name: STATUS Offset: 0x0F Reset: 0x08 Property: - Bit 7 6 5 SYNCBUSY 4 3 SLAVE STOP 2 1 0 Access R R R R R R R R Reset 0 0 0 0 1 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:5 – Reserved These bits are unused and reserved for future use.
27.8.12 Counter Value 27.8.12.1 8-Bit Mode Name: COUNT Offset: 0x10 Reset: 0x00 Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – COUNT[7:0]: Counter Value These bits contain the current counter value.
27.8.12.2 16-Bit Mode Name: COUNT Offset: 0x10 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0]: Counter Value These bits contain the current counter value.
27.8.12.
27.8.13 Period Value The Period Value register is available only in 8-bit TC mode. It is not available in 16-bit and 32-bit TC modes. 27.8.13.1 8-Bit Mode Name: PER Offset: 0x14 Reset: 0xFF Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 PER[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:0 – PER[7:0]: Period Value These bits contain the counter period value in 8-bitTC mode.
27.8.14 Compare/Capture 27.8.14.1 8-Bit Mode Name: CCx Offset: 0x18+i*0x1 [i=0..3] Reset: 0x00 Property: Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 CC[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – CC[7:0]: Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In frequency or PWM waveform match operation (CTRLA.WAVEGEN), the CC0 register is used as a period register.
27.8.14.2 16-Bit Mode Name: CCx Offset: 0x18+i*0x2 [i=0..3] Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 CC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – CC[15:0]: Compare/Capture Value These bits contain the compare/capture value in 16-bit TC mode.
27.8.14.3 32-Bit Mode Name: CCx Offset: 0x18+i*0x4 [i=0..
28. 28.1 ADC – Analog-to-Digital Converter Overview The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution, and is capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended measurements can be performed. An optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
z Event-triggered conversion for accurate timing (one event input) z Hardware gain and offset compensation z Averaging and oversampling with decimation to support, up to 16-bit result z Selectable sampling time 28.3 Block Diagram Figure 28-1. ADC Block Diagram CTRLA WINCTRL AVGCTRL WINLT SAMPCTRL WINUT EVCTRL OFFSETCORR SWTRIG GAINCORR INPUTCTRL ADC0 ... ADCn INT.SIG ADC POST PROCESSING RESULT ADC0 ... ADCn INT.SIG INT1V CTRLB INTVCC VREFA VREFB PRESCALER REFCTRL 28.
28.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT). Refer to “PORT” on page 280 for details. 28.5.2 Power Management The ADC will continue to operate in any sleep mode where the selected source clock is running. The ADC’s interrupts can be used to wake up the device from sleep modes.
28.5.10 Calibration The values BIAS_CAL and LINEARITY_CAL from the production test must be loaded from the NVM Software Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy. Refer to “NVM Software Calibration Area Mapping” on page 23 for more details. 28.6 Functional Description 28.6.1 Principle of Operation By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce the conversion time.
28.6.3 Prescaler The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates. Refer to CTRLB for details on prescaler settings. Figure 28-2. ADC Prescaler DIV512 DIV256 DIV128 DIV64 DIV32 DIV16 DIV8 9-BIT PRESCALER DIV4 GCLK_ADC CTRLB.
28.6.5 Differential and Single-Ended Conversions The ADC has two conversion options: differential and single-ended. When measuring signals where the positive input is always at a higher voltage than the negative input, the single-ended conversion should be used in order to have full 12bit resolution in the conversion, which has only positive values. The negative input must be connected to ground. This ground could be the internal GND, IOGND or an external ground connected to a pin.
Figure 28-5. ADC Timing for Free Running in Differential Mode without Gain 2 1 3 4 5 6 7 9 8 10 11 12 13 6 4 2 0 14 15 16 8 6 CLK_ ADC START SAMPLE INT Converting Bit 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 5 3 1 11 10 9 7 5 Figure 28-6. ADC Timing for One Conversion in Single-Ended Mode without Gain 1 2 3 4 5 6 7 8 9 10 11 CLK_ADC START SAMPLE AMPLIFY INT Converting Bit MS B 10 9 8 7 6 5 4 3 2 1 LS B Figure 28-7.
28.6.6 Accumulation The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is specified by writing to the Number of Samples to be Collected field in the Average Control register (AVGCTRL.SAMPLENUM) as described in Table 28-2. When accumulating more than 16 samples, the result will be too large for the 16-bit RESULT register. To avoid overflow, the result is shifted right automatically to fit within the 16 available bits.
Table 28-3. Averaging Number of Accumulated Samples AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Division Factor AVGCTRL.
Another important point is that the significant WINLT and WINUT bits are given by the precision selected in the Conversion Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means that if 8-bit mode is selected, only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit even if the ninth bit is zero. The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition. 28.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR) register.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is stalled. The following bits need synchronization when written: z Software Reset bit in the Control A register (CTRLA.SWRST) z Enable bit in the Control A register (CTRLA.
28.7 Register Summary Offset Name Bit pos.
Offset Name 0x24 Bit pos.
28.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 476 for details.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
28.8.2 Reference Control Name: REFCTRL Offset: 0x01 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 REFCOMP Access Reset z 1 0 REFSEL[3:0] R/W R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – REFCOMP: Reference Buffer Offset Compensation Enable The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference.
28.8.3 Average Control Name: AVGCTRL Offset: 0x02 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 ADJRES[2:0] 2 1 0 SAMPLENUM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
28.8.4 Sampling Time Control Name: SAMPCTRL Offset: 0x03 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SAMPLEN[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
28.8.5 Control B Name: CTRLB Offset: 0x04 Reset: 0x0000 Property: Write-Synchronized, Write-Protected Bit 15 14 13 12 11 10 9 8 PRESCALER[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CORREN FREERUN LEFTADJ DIFFMODE RESSEL[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:11 – Reserved These bits are unused and reserved for future use.
Table 28-8. Conversion Result Resolution Value Name Description 0x0 12BIT 12-bit result 0x1 16BIT For averaging mode output 0x2 10BIT 10-bit result 0x3 8BIT 8-bit result z Bit 3 – CORREN: Digital Correction Logic Enabled 0: Disable the digital result correction. 1: Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers.
28.8.6 Window Monitor Control Name: WINCTRL Offset: 0x08 Reset: 0x00 Property: Write-Synchronized, Write-Protected Bit 7 6 5 4 3 2 1 0 WINMODE[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
28.8.7 Software Trigger Name: SWTRIG Offset: 0x0C Reset: 0x00 Property: Write-Synchronized, Write-Protected Bit 7 6 5 4 3 2 1 0 START FLUSH Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
28.8.
Table 28-10. Gain Factor Selection Value Name Description 0x0 1X 1x 0x1 2X 2x 0x2 4X 4x 0x3 8X 8x 0x4 16X 16x 0x5-0xE – Reserved 0xF DIV2 1/2x z Bits 23:20 – INPUTOFFSET[3:0]: Positive Mux Setting Offset The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET.
Table 28-11. Negative Mux Input Selection (Continued) Value Name Description 0x02 PIN2 ADC AIN2 pin 0x03 PIN3 ADC AIN3 pin 0x04 PIN4 ADC AIN4 pin 0x05 PIN5 ADC AIN5 pin 0x06 PIN6 ADC AIN6 pin 0x07 PIN7 ADC AIN7 pin 0x08-0x17 – Reserved 0x18 GND Internal ground 0x19 IOGND I/O ground 0x1A-0x1F – Reserved z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Table 28-12.
28.8.9 Event Control Name: EVCTRL Offset: 0x14 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 WINMONEO RESRDYEO 3 2 1 0 SYNCEI STARTEI Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
28.8.10 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x16 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use.
28.8.11 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x17 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use.
28.8.12 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
28.8.13 Status Name: STATUS Offset: 0x19 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
28.8.14 Result Name: RESULT Offset: 0x1A Reset: 0x0000 Property: Read-Synchronized Bit 15 14 13 12 11 10 9 8 RESULT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 – RESULT[15:0]: Result Conversion Value These bits will hold up to a 16-bit ADC result, depending on the configuration.
28.8.15 Window Monitor Lower Threshold Name: WINLT Offset: 0x1C Reset: 0x0000 Property: Write-Synchronized, Write-Protected Bit 15 14 13 12 11 10 9 8 WINLT[15:8] Acces s R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINLT[7:0] Acces s R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:0 – WINLT[15:0]: Window Lower Threshold If the window monitor is enabled, these bits define the lower threshold value.
28.8.16 Window Monitor Upper Threshold Name: WINUT Offset: 0x20 Reset: 0x0000 Property: Write-Synchronized, Write-Protected Bit 15 14 13 12 11 10 9 8 WINUT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINUT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – WINUT[15:0]: Window Upper Threshold If the window monitor is enabled, these bits define the upper threshold value.
28.8.17 Gain Correction Name: GAINCORR Offset: 0x24 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 GAINCORR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GAINCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 – Reserved These bits are unused and reserved for future use.
28.8.18 Offset Correction Name: OFFSETCORR Offset: 0x26 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 OFFSETCORR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OFFSETCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 – Reserved These bits are unused and reserved for future use.
28.8.19 Calibration Name: CALIB Offset: 0x28 Reset: 0x0000 Property: Write-Protected Bit 15 14 13 12 11 10 9 8 BIAS_CAL[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LINEARITY_CAL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:11 – Reserved These bits are unused and reserved for future use.
28.8.20 Debug Control Name: DBGCTRL Offset: 0x2A Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 DBGRUN Access R R R R R R R R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 0 – DBGRUN: Debug Run 0: The ADC is halted during debug mode.
29. 29.1 AC – Analog Comparators Overview The Analog Comparator (AC) supports two individual comparators. Each comparator (COMP) compares the voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be configured to generate interrupt requests and/or peripheral events upon several different combinations of input change. Hysteresis and propagation delay are two important properties of the comparators; dynamic behavior.
29.3 Block Diagram Figure 29-1. Analog Comparator Block Diagram AIN0 + CMP0 COMP0 AIN1 - HYSTERESIS VDDANA SCALER INTERRUPTS ENABLE INTERRUPT MODE DAC COMPCTRLn WINCTRL ENABLE BANDGAP EVENTS GCLK_AC HYSTERESIS + AIN2 INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION CMP1 COMP1 AIN3 29.4 - Signal Description Signal Name Type Description AIN[3..0] Analog input Comparator inputs CMP[1..
29.5.2 Power Management The AC will continue to operate in any sleep mode where the selected source clock is running. The AC’s interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes. 29.5.
29.6 Functional Description 29.6.1 Principle of Operation Each comparator has one positive input and one negative input. Each positive input may be chosen from a selection of analog input pins. Each negative input may be chosen from a selection of analog input pins or internal inputs, such as a bandgap reference voltage. The digital output from the comparator is one when the difference between the positive and the negative input voltage is positive, and zero otherwise.
of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of whether the interrupt is enabled or not. Continuous Measurement Continuous measurement is selected by writing COMPCTRLx.SINGLE to zero. In continuous mode, the comparator is continuously enabled and performing comparisons.
Figure 29-3. Single-Shot Example GCLK_AC Write ‘1’ CTRLB.STARTx Write ‘1’ 2-3 cycles 2-3 cycles tSTARTUP tSTARTUP STATUSB.READYx Sampled Comparator Output For low-power operation, event-triggered measurements can be performed during sleep modes. When the event occurs, the Power Manager will start GCLK_AC_DIG. The comparator is enabled, and after the startup time has passed, a comparison is done and appropriate peripheral events and interrupts are also generated.
Figure 29-4. Comparators in Window Mode + STATE0 COMP0 UPPER LIMIT OF WINDOW - WSTATE[1:0] INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION INPUT SIGNAL INTERRUPTS EVENTS + STATE1 COMP1 LOWER LIMIT OF WINDOW - 29.6.5 Voltage Doubler The AC contains a voltage doubler that can reduce the resistance of the analog multiplexors when the supply voltage is below 2.5V. The voltage doubler is normally switched on/off automatically based on the supply level.
Figure 29-5. VDDANA Scaler COMPCTRLx.MUXNEG == 5 SCALERx. VALUE 6 to COMPx 29.6.7 Input Hysteresis Application software can selectively enable/disable hysteresis for the comparison. Applying hysteresis will help prevent constant toggling of the output, which can be caused by noise when the input signals are close to each other. Hysteresis is enabled for each comparator individually by the Hysteresis Mode bit in the Comparator x Control register (COMPCTRLx.HYST).
Figure 29-6. Continuous Mode Filtering Sampling Clock Sampled Comparator Output 3-bit Majority Filter Output 5-bit Majority Filter Output Figure 29-7. Single-Shot Filtering Sampling Clock Start t SUT 3-bit Sampled Comparator Output 3-bit Majority Filter Output 5-bit Sampled Comparator Output 5-bit Majority Filter Output During sleep modes, filtering is supported only for single-shot measurements.
29.7 Additional Features 29.7.1 Interrupts The peripheral has the following interrupt sources: z Comparator: COMP0, COMP1(INTENCLR, INTSET, INTFLAG) z Window: WIN0(INTENCLR, INTSET, INTFLAG) Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.
analog blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system returns from sleep. When RUNSTDBY is one, any enabled AC interrupt source can wake up the CPU. While the CPU is sleeping, singleshot comparisons are only triggerable by events. The AC can also be used during sleep modes where the clock used by the AC is disabled, provided that the AC is still powered (not in shutdown).
z Synchronization when written z Synchronization when read z Synchronization when written and read z No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled.
29.8 Register Summary Offset Name Bit Pos.
29.9 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 515 for details.
z Bit 0 – SWRST: Software Reset 0: There is no reset operation ongoing. 1: The reset operation is ongoing. Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the AC to their initial state, and the AC will be disabled. Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and STATUS.
29.9.2 Control B Name: CTRLB Offset: 0x01 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 1 0 START1 START0 Access R R R R R R W W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 1:0 – STARTx: Comparator x Start Comparison Writing a zero to this field has no effect.
29.9.3 Event Control Name: EVCTRL Offset: 0x02 Reset: 0x0000 Property: Write-Protected, Enable-Protected Bit 15 14 13 12 11 10 9 8 COMPEI1 COMPEI0 Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMPEO1 COMPEO0 WINEO0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:10 – Reserved These bits are unused and reserved for future use.
29.9.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x04 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use.
29.9.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x05 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use.
29.9.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x06 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 WIN0 1 0 COMP1 COMP0 Access R R R R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
29.9.7 Status A Name: STATUSA Offset: 0x08 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 WSTATE0[1:0] 1 0 STATE1 STATE0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
29.9.8 Status B Name: STATUSB Offset: 0x09 Reset: 0x00 Property: – Bit 7 6 5 4 3 2 SYNCBUSY 1 0 READY1 READY0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:2 – Reserved These bits are unused and reserved for future use.
29.9.9 Status C STATUSC is a copy of STATUSA (see STATUSA register), with the additional feature of automatically starting singleshot comparisons. A read of STATUSC will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be started.
29.9.10 Window Control Name: WINCTRL Offset: 0x0C Reset: 0x00 Property: Write-Synchronized, Write-Protected Bit 7 6 5 4 3 2 1 WINTSEL0[1:0] 0 WEN0 Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
29.9.11 Scaler n Name: SCALERn Offset: 0x20+n*0x1 [n=0..1] Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 VALUE[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
29.9.12 Comparator Control n The configuration of comparator n is protected while comparator n is enabled (COMPCTRLn.ENABLE = 1). Changes to the other bits in COMPCTRLn can only occur when COMPCTRLn.ENABLE is zero. Name: COMPCTRLn Offset: 0x10+n*0x4 [n=0..
Table 29-5. Filter Length Value Name Description 0x0 OFF No filtering 0x1 MAJ3 3-bit majority function (2 of 3) 0x2 MAJ5 5-bit majority function (3 of 5) 0x3-0x7 N/A Reserved z Bits 23:20 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 19 – HYST: Hysteresis Enable This bit indicates the hysteresis mode of comparator n.
z Bit 14 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 13:12 – MUXPOS[1:0]: Positive Input Mux Selection These bits select which input will be connected to the positive input of comparator n. COMPCTRLn.MUXPOS can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized. Table 29-7.
Table 29-9. Interrupt Selection Value Name Description 0x0 TOGGLE Interrupt on comparator output toggle 0x1 RISING Interrupt on comparator output rising 0x2 FALLING Interrupt on comparator output falling 0x3 EOC Interrupt on end of comparison (single-shot mode only) z Bit 4 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read.
30. 30.1 DAC – Digital-to-Analog Converter Overview The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC has one channel with 10-bit resolution, and it is capable of converting up to 350,000 samples per second (350ksps). 30.2 Features z DAC with 10-bit resolution z Up to 350ksps conversion rate z Multiple trigger sources z High-drive capabilities z Output can be used as input to the Analog Comparator (AC) 30.3 Block Diagram Figure 30-1.
30.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines Using the DAC’s I/O lines requires the I/O pins to be configured using the port configuration (PORT). Refer to “PORT” on page 280 for details. 30.5.2 Power Management The DAC will continue to operate in any sleep mode where the selected source clock is running. The DAC interrupts can be used to wake up the device from sleep modes.
30.6 Functional Description 30.6.1 Principle of Operation The Digital-to-Analog Converter (DAC) converts the digital value written to the Data register (DATA) into an analog voltage on the DAC output. By default, a conversion is started when new data is written to DATA, and the corresponding voltage is available on the DAC output after the conversion time. It is also possible to enable events from the Event System to trigger the conversion. 30.6.2 Basic Operation 30.6.2.
The DAC can generate a Data Buffer Empty event when DATABUF becomes empty and new data can be loaded to the buffer. The Data Buffer Empty event is enabled by writing a one to the Empty Event Output bit in the Event Control register (EVCTRL.EMPTYEO). A Data Buffer Empty interrupt request is generated if the Data Buffer Empty interrupt is enabled. 30.6.3.4 Voltage Pump When the DAC is used at operating voltages lower than 2.5V, the voltage pump must be enabled.
connected to the DAC, the enabled action will be taken on any of the incoming events. Refer to “EVSYS – Event System” on page 306 for details on configuring the event system. 30.6.7 Sleep Mode Operation The generic clock for the DAC is running in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the DAC output buffer will keep its value in standby sleep mode. If CTRLA.RUNSTDBY is zero, the DAC output buffer will be disabled in standby sleep mode. 30.6.
30.7 Register Summary Offset Name Bit Pos.
30.8 Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 543 for details.
30.8.1 Control A Name: CTRLA Offset: 0x0 Reset: 0x00 Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 RUNSTDBY ENABLE SWRST Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
30.8.2 Control B Name: CTRLB Offset: 0x1 Reset: 0x00 Property: Write-Protected Bit 7 6 5 REFSEL[1:0] Access Reset z 4 3 2 1 0 - VPD LEFTADJ IOEN EOEN R/W R/W R R R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:6 – REFSEL[1:0]: Reference Selection These bits select the reference voltage for the DAC according to Table 30-1. Table 30-1. Reference Selection REFSEL[1:0] Reference Selection Description 0x0 INT1V Internal 1.
30.8.3 Event Control Name: EVCTRL Offset: 0x2 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 EMPTYEO STARTEI Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
30.8.4 Interrupt Enable Clear This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Name: INTENCLR Offset: 0x4 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY EMPTY UNDERRUN Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
30.8.5 Interrupt Enable Set This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Name: INTENSET Offset: 0x5 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY EMPTY UNDERRUN Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use.
30.8.6 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x6 Reset: 0x00 Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY EMPTY UNDERRUN Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read.
30.8.7 Status Name: STATUS Offset: 0x7 Reset: 0x00 Property: Read-Synchronized Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use.
30.8.8 Data Name: DATA Offset: 0x8 Reset: 0x0000 Property: Write-Synchronized, Read-Synchronized, Write-Protected Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – DATA: Data value to be converted DATA register contains the 10-bit value that is converted to a voltage by the DAC.
30.8.9 Data Buffer Name: DATABUF Offset: 0xC Reset: 0x0000 Property: Write-Synchronized, Write-Protected Bit 15 14 13 12 11 10 9 8 DATABUF[15:8] Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATABUF[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – DATABUF: Data Buffer DATABUF contains the value to be transferred into DATA register.
31. PTC - Peripheral Touch Controller 31.1 Overview The purpose of PTC is to acquire signals to detect touch on capacitive sensors. The external capacitive touch sensor is typically formed on a PCB, and the sensor electrodes are connected to the analog front end of the PTC through the I/O pins in the device. The PTC supports both self- and mutual-capacitance sensors.
31.3 Block Diagram Figure 31-1. PTC Block Diagram Mutual-capacitance Input control Y0 Y1 Y15 Compensation Circuit RS 100K Acquisition Module •Gain control •ADC •Filtering IRQ Result 10 X0 X1 X Line Driver X15 Figure 31-2.
31.4 Signal Description Name Type Description X[n:0] Digital X-line (Output) Y[m:0] Analog Y-line (Input/Output) Note: 1. The number of X and Y lines are device dependent. Refer to “Configuration Summary” on page 3 for details. Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal can be mapped on several pins. 31.
Self-capacitance Sensor Arrangement The self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for receiving the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller. Figure 31-4. Self-capacitance Sensor Arrangement MCU Sensor Capacitance Cy Y0 Cy0 Y1 PTC Module Ym Cy1 Cym For more information about designing the touch sensor, refer to Buttons, Sliders and Wheels Touch Sensor Design Guide on http://www.atmel.
31.6 Functional Description In order to access the PTC, the user must use the QTouch Composer tool to configure and link the QTouch Library firmware with the application code. QTouch Library can be used to implement buttons, sliders, wheels and proximity sensor in a variety of combinations on a single interface. For more information about QTouch library, refer to the Atmel QTouch Library Peripheral Touch Controller User Guide. Figure 31-5.
32. Electrical Characteristics 32.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 32.2 Absolute Maximum Ratings Stresses beyond those listed in Table 32-1 may cause permanent damage to the device.
Table 32-2. GPIO Clusters PACKAGE CLUSTER 64pins 48pins 32pins 32.
32.4 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are valid for a junction temperature up to TJ = 100°C. Refer to “Power Supply and Start-Up Considerations” on page 16. Table 32-4. Supply Characteristics Voltage Symbol Conditions Min. Max. Units VDDIO VDDIN VDDANA Full Voltage Range 1.62 3.63 V Table 32-5. Supply Rise Rates Rise Rate 32.
Table 32-6.
32.6 Power Consumption The values in Table 32-7 are measured values of power consumption under the following conditions, except where noted: z Operating conditions z VVDDIN = 3.3V z Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first instruction fetched in flash.
Table 32-7. Current Consumption Mode Conditions TA Min. Typ. Max. 25°C 2.13 2.33 2.52 85°C 2.24 2.44 2.63 CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states 25°C 2.13 2.34 2.53 85°C 2.26 2.45 2.64 CPU running a While(1) algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25°C - 42*freq +118 - 85°C - 42*freq +208 - 25°C 3.63 4.03 4.37 85°C 3.74 4.12 4.44 25°C 3.64 4.03 4.37 wait states 85°C 3.76 4.
Table 32-8. Wake-up Time Mode Conditions IDLE0 IDLE1 TA Min. Typ. Max. OSC8M used as main clock source, low power cache disabled 25°C 3.3 4.0 4.5 85°C 3.4 4.0 4.5 OSC8M used as main clock source, low power cache disabled 25°C 10.5 12.1 13.7 85°C 12.1 13.6 15.0 25°C 11.7 13.0 14.3 85°C 13.0 14.5 15.9 25°C 17.5 19.6 21.4 85°C 18.0 19.7 21.
32.7 I/O Pin Characteristics 32.7.1 Normal I/O Pins Table 32-9. RevD and later normal I/O Pins Characteristics Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage IOL Conditions Min. Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7V - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - VDD>1.6V, IOL maxI - 0.
Table 32-10. SAMD20 revC/revB Normal I/O Pins Characteristics Symbol Parameter Conditions Min. Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7V - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VDD>1.6V, IOL maxI - 0.1*VDD 0.2*VDD VOH Output high-level voltage VDD>1.6V, IOH maxI 0.8*VDD 0.
32.7.2 I2C Pins Refer to “I/O Multiplexing and Considerations” on page 11 to get the list of I2C pins. Table 32-11. I2C Pins Characteristics in I2C configuration Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VHYS Hysteresis of Schmitt trigger inputs VOL Output low-level voltage IOL Output low-level current fSCL SCL clock frequency Condition Min. Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7VI - - 0.25*VDD VDD=2.7V-3.
32.8 Analog Characteristics 32.8.1 Voltage Regulator Characteristics Table 32-12. Voltage Regulator Electrical Characteristics Symbol VDDCORE Note: Parameter DC calibrated output voltage Conditions Min. Typ. Max. Units Voltage regulator normal mode 1.1 1.23 1.30 V Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core supply voltage. Table 32-13.
32.8.3 Brown-Out Detectors Characteristics 32.8.3.1 BOD33 Table 32-15. BOD33 LEVEL Value BOD33.LEVEL Conditions Min. Typ. Max. - 1.715 1.745 - 1.750 1.779 39 - 2.84 2.92 48 - 3.2 3.3 6 1.62 1.64 1.67 1.64 1.675 1.71 39 2.72 2.77 2.81 48 3.0 3.07 3.2 6 7 Units Hysteresis on V 7 Hysteresis off Note: See chapter Memories table “NVM User Row Mapping” for the BOD33 default value settings. Table 32-16. BOD33 Characteristics Symbol Parameter Conditions Min. Typ. Max.
Table 32-17. Operating Conditions (Continued) Symbol Parameter Conditions Sampling time(1) Conversion time(1) 1x Gain Min. Typ. Max. Units 0.5 - - cycles - 6 - cycles VREF Voltage reference range 1.0 - VDDANA-0.6 V VREFINT1V Internal 1V reference (2) - 1.0 - V VREFINTVCC0 Internal ratiometric reference 0(2) - VDDANA/1.48 - V VREFINTVCC1 Internal ratiometric reference 1(2) - VDDANA/2 - V -VREF/GAIN - +VREF/GAIN V 0.0 - +VREF/GAIN V - 3.5 - pF - - 3.
Symbol 4. Min. Typ. Max. Units 62.7 70.0 75.0 dB Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion FCLK_ADC = 2.1MHz 54.1 65.0 68.5 dB Signal-to-Noise Ratio FIN = 40kHz 54.5 65.5 68.6 dB Total Harmonic Distortion AIN = 95%FSR -77.0 -64.0 -63.0 dB Noise RMS T=25°C 0.6 1.0 1.6 mV THD 1. 2. 3.
32.8.4.1 Performance with the Averaging Digital Feature Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-becollected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT). Table 32-20.
Figure 32-3. ADC Input VDDANA/2 Analog Input AINx RSOURCE CSAMPLE RSAMPLE VIN To achieve n bits of accuracy, the C SAMPLE capacitor must be charged at least to a voltage of V CSAMPLE ≥ V IN × ( 1 – 2 –( n + 1 ) The minimum sampling time ) t SAMPLEHOLD for a given R SOURCE can be found using this formula: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × ( n + 1 ) × ln ( 2 ) for a 12 bits accuracy: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × 9.
Table 32-23. Clock and Timing(1) Symbol Parameter Conditions Conversion rate Startup time I Note: 1. Min. Typ. Max. Units Cload=100pF Normal mode - - 350 Rload > 5kΩ For ΔDATA=+/-1 - - 1000 VDDNA > 2.6V - - 2.85 µs VDDNA < 2.6V - - 10 µs ksps These values are based on simulation. These values are not covered by test limits in production or characterization. Table 32-24.
Symbol Parameter Conditions Min. Typ. Max. Units Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.0 +25 mV Hysteresis = 1, Fast mode 20 50 80 mV Hysteresis = 1, Low power mode 15 40 75 mV Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 60 116 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode - 225 370 ns Enable to ready delay Fast mode - 1 2 µs Enable to ready delay Low power mode - 12 19 µs -1.4 0.75 +1.
32.8.8 Temperature Sensor Characteristics 32.8.8.1 Temperature Sensor Characteristics Table 32-27. Temperature Sensor Characteristics(1)) Symbol Parameter Conditions Temperature sensor output voltage I I Temperature sensor slope I Variation over VDDANA voltage Note: 1. 2. T= 25°C, VDDANA = 3.3V VDDANA=1.62V to 3.6V Min. Typ. Max. Units - 0.667 - V 2.3 2.4 2.5 mV/°C -1.7 1 3.7 mV/V These values are based on characterization.
Bit Position Name Description 39:32 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot temperature (versus a 1.
⎛ V ADC – V ADCR⎞ ⎛ V ADCH – V ADCR⎞ ⎜ ---------------------------------------⎟ = ⎜ -------------------------------------------⎟ ⎝ temp – temp R ⎠ ⎝ temp H – temp R ⎠ Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as: ⎧ ⎫ INT1V R ⎞ ⎪ ⎞ ⎛ ⎪⎛ 1 -⎟ – ⎜ ADC R ⋅ ----------------------⎟ ⎬ ⋅ ( temp H – temp R ) ⎨ ⎜ ADC m ⋅ --------------------12 12 ⎝ ⎪ ( 2 – 1 )⎠ ⎝ ( 2 – 1 )⎠ ⎪ ⎩ ⎭ temp C = temp R + ------------------------------------------------------
⎛ ( INT1V H – INT1V R ) ⋅ ( temp C – temp R )⎞ INT1V m = INT1V R + ⎜ ----------------------------------------------------------------------------------------------------⎟ ( temp H – temp R ) ⎝ ⎠ Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature value as: INT1V m ⎞ ⎛ INT1V R ⎞ ⎫ ⎧⎛ -----------------------------------------⎟ ⎬ ⋅ ( temp H – temp R ) – ADC ADC ⋅ ⋅ ⎜ ⎟ ⎜ ⎨ m R 12 12 ⎝ ⎠ ⎝ ⎩ (2 – 1) ( 2 – 1 )⎠ ⎭ temp f = temp R + --------------------------------
32.9 NVM Characteristics Table 32-29. Maximum Operating Frequency VDD range NVM Wait States Maximum Operating Frequency 0 14 1 28 2 42 3 48 0 24 1 48 Units 1.62V to 2.7V MHz 2.7V to 3.63V Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 32-30. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max.
32.10 Oscillators Characteristics 32.10.1 Crystal Oscillator (XOSC) Characteristics 32.10.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 32-33. Digital Clock Characteristics Symbol fCPXIN Parameter Conditions XIN clock frequency I Min. Typ. Max. Units - - 32 MHz 32.10.1.
Symbol Parameter Conditions Current Consumption tSTARTUP Startup time Min. Typ. Max.
32.10.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics 32.10.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 32-35. Digital Clock Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fCPXIN32 XIN32 clock frequency I - 32.768 - kHz I XIN32 clock duty cycle I - 50 - % 32.10.2.
Symbol Parameter Conditions Min. Typ. Max. Units µA IDFLL Power consumption on VDDANA Open loop, Coarse calibrated against 48MHz, FINE=128 - 100 - tSTARTUP Startup time Open loop after calibration against 48MHz fOUT within 90% of final value - 8 - Fine lock time Quick lock disabled, Chill cycle disabled, CSTEP=3,FSTEP=1, fREF = 32.768kHz tLFINE Note: 1. 2. µs - 600 - These values are based on simulation.
Symbol Parameter Conditions iOSCULP32K (1)(2) Min. Typ. Max. Units - - 125 nA tSTARTUP Startup time I - 10 - cycles Duty Duty Cycle I - 50 - % Units Notes: 1. 2. These values are based on simulation. These values are not covered by test limits in production or characterization. This oscillator is always on. 32.10.6 8MHz RC Oscillator (OSC8M) Characteristics Table 32-40. Internal 8MHz RC Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max.
32.11 PTC Typical Characteristics Figure 32-5. Power consumption [µA]. 1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V 140 120 100 80 Scan rate 10ms 60 Scan rate 50ms 40 Scan rate 100ms Scan rate 200ms 20 0 1 2 4 8 16 32 64 Sample averaging Figure 32-6. Power consumption [µA]. 1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.
Figure 32-7. Power consumption [µA]. 10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 1200 1000 800 Scan rate 10ms 600 Scan rate 50ms Scan rate 100ms 400 Scan rate 200ms 200 Linear (Scan rate 50ms) 0 1 2 4 8 16 32 64 Sample averaging Figure 32-8. Power consumption [µA]. 10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.
Figure 32-9. Power consumption [µA]. 100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 5000 4500 4000 3500 3000 Scan rate 10ms 2500 2000 Scan rate 50ms 1500 Scan rate 100ms 1000 Scan rate 200ms 500 0 1 2 4 8 16 32 64 Sample averaging Figure 32-10.Power consumption [µA]. 100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.
Figure 32-11.CPU utilization.
32.12 Timing Characteristics 32.12.1 External Reset Table 32-41. External reset characteristics Symbol tEXT Parameter Condition Minimum reset pulse width I Min. Typ. Max. Units 10 - - ns 32.12.2 SERCOM in SPI Mode Timing Figure 32-12.
Figure 32-13.
Table 32-42. SPI timing characteristics and requirements(1) Symbol Parameter tSCK SCK period Master Refer to section 25.6.2.3 Clock Generation tSCKW SCK high/low width Master - 0.
32.12.3 SERCOM in I2C Mode Timing Table 32-43 describes the requirements for devices connected to the I2C Interface Bus. Timing symbols refer to Figure 32-14. Figure 32-14.I2C Interface Bus Timing tOF tHIGH tR tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF Table 32-43. I2C Interface Timing(1) Symbol Parameter Conditions Min. Typ. Max. - - 300 tR Rise time for both SDA and SCL (3) I tOF Output fall time from VIHmin to VILmax (3) 10pF < Cb(2) < 400pF 7.0 10.0 50.
32.12.4 SWD Timing Figure 32-15.SWD Interface Signals Read Cycle From debugger to SWDIO pin Stop Park Tri State Thigh Tos Data Data Parity Start Tlow From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Tri State Write Cycle From debugger to SWDIO pin Stop Park Tri State Tis Start Tih From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Data Data Parity Tri State Table 32-44. SWD Timings(1) Symbol Parameter Conditions Min. Max.
33. Packaging Information 33.1 Thermal Considerations 33.1.1 Thermal Resistance Data Table 33-1 summarizes the thermal resistance data depending on the package. Table 33-1. Thermal Resistance Data Package Type θJA θJC 32-pin TQFP 68°C/W 25.8°C/W 48-pin TQFP 78.8°C/W 12.3°C/W 64-pin TQFP 66.7°C/W 11.9°C/W 32-pin QFN 37.2°C/W 3.1°C/W 48-pin QFN 33°C/W 11.4°C/W 64-pin QFN 33.5°C/W 11.2°C/W 33.1.
33.2 Package Drawings 33.2.1 64-pin TQFP Table 33-2. Device and Package Maximum Weight 300 mg Table 33-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-4.
33.2.2 64-pin QFN Note: The exposed die attached pad is not connected inside the device. Table 33-5. Device and Package Maximum Weight 200 mg Table 33-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-7.
33.2.3 48-pin TQFP Table 33-8. Device and Package Maximum Weight 140 mg Table 33-9. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-10.
33.2.4 48-pin QFN Note: The exposed die attached pad is not connected inside the device. Table 33-11. Device and Package Maximum Weight 140 mg Table 33-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-13.
33.2.5 32-pin TQFP Table 33-14. Device and Package Maximum Weight 100 mg Table 33-15. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-16.
33.2.6 32-pin QFN Note: The exposed die attached pad is connected inside the device to GND and GNDANA connected together. Table 33-17. Device and Package Maximum Weight 90 mg Table 33-18. Package Characteristics Moisture Sensitivity Level MSL3 Table 33-19.
33.3 Soldering Profile Table Table 33-20 gives the recommended soldering profile from J-STD-20. Table 33-20. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max. Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature 60-150s 30s 260°C 6°C/s max 8 minutes max. A maximum of three reflow passes is allowed per component.
34. Schematic Checklist 34.1 Introduction This chapter describes a common checklist which should be used when starting and reviewing the schematics for a SAM D20 design. This chapter illustrates a recommended power supply connection, how to connect external analog references, programmer, debugger, oscillator and crystal. 34.2 Power Supply The SAM D20 supports a single power supply from 1.62 to 3.63V. 34.2.1 Power Supply Connections Figure 34-1.
Table 34-1. Power Supply Connections, VDDCORE From Internal Regulator (Continued) Signal Name Recommended Pin Connection Description VDDCORE 1.6V to 1.8V Decoupling/filtering capacitor 100nF(1)(2) Core supply voltage / external decoupling pin GND Ground GNDANA Ground for the analog power domain Notes: 1. 2. 3. 4. 34.3 These values are only given as typical examples.
Figure 34-3. External Analog Reference Schematic With One Reference Close to device (for every pin) AREFA EXTERNAL REFERENCE 4.7µF 100nF GND AREFB 100nF GND Table 34-2. External Analog Reference Connections Signal Name Recommended Pin Connection Description AREFx 1.0V to VDDANA - 0.6V for ADC 1.0V to VDDANA - 0.6V for DAC Decoupling/filtering capacitors 100nF(1)(2) and 4.7µF(1) External reference from AREFx pin on the analog port GND Ground Notes: 1. 2.
34.4 External Reset Circuit The external reset circuit is connected to the RESET pin when the external reset function is used. If the external reset function has been disabled, the circuit is not necessary. The reset switch can also be removed, if the manual reset is not necessary. The RESET pin itself has an internal pull-up resistor, hence it is optional to also add an external pull-up resistor. Figure 34-4.
resistors can be used, e.g. the pins can be configured in pull-up or pull-down mode eliminating the need for external components, for more information see “PORT” on page 280 for details. There are no obvious benefit in choosing external vs. internal pull resistors. 34.6 Clocks and Crystal Oscillators The SAM D20 can be run from internal or external clock sources, or a mix of internal and external sources.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. 34.6.3 External Real Time Oscillator The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are specified by the crystal vendor.
34.6.4 Calculating the Correct Crystal Decoupling Capacitor In order to calculate correct load capacitor for a given crystal one can use the model shown in Figure 34-9 which includes internal capacitors CLn, external parasitic capacitance CELn and external load capacitance CPn. Figure 34-9.
Table 34-8. Equivalent Internal Pin Capacitance 34.7 Symbol Value Description CXIN32 3.05pF Equivalent internal pin capacitance CXOUT32 3.29pF Equivalent internal pin capacitance Programming and Debug Ports For programming and/or debugging the SAM D20 the device should be connected using the Serial Wire Debug, SWD, interface.
Header Signal Name Description RESET Target device reset pin, active low VTref Target voltage sense, should be connected to the device VDD GND Ground Atmel | SMART SAM D20 [DATASHEET] Atmel-42129K–SAM-D20_datasheet–06/2014 616
34.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug Interface The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a special pinout is needed to directly connect the SAM D20 to the JTAGICE3, alternatively one can use the JTAGICE3 squid cable and manually match the signals between the JTAGICE3 and SAM D20. Figure 34-11 describes how to connect a 10-pin header that support connecting the JTAGICE3 directly to the SAM D20 without the need for a squid cable.
34.7.3 20-pin IDC JTAG Connector For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals should be connected as shown in Figure 34-12 with details described in Table 34-11. Figure 34-12.20-pin IDC JTAG Connector VDD 20-pin IDC JTAG Connector VCC 1 NC NC GND NC GND SWDIO GND SWDCLK GND NC GND NC GND* nRESET GND* NC GND* NC GND* RESET SWCLK SWDIO GND Table 34-11.
35. Errata 35.1 Revision D 35.1.1 NVMCTRL 1 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 35.1.2 Device 1 - After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.
Set the voltage regulator in Normal mode before entering STANDBY sleep mode in order to keep digital pin output enabled. This is done by setting the RUNSTDBY bit in the VREG register. 5 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 35.1.
35.2 Revision C 35.2.1 NVMCTRL 1 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 35.2.
4 - The PORT output driver strength feature is not available. Errata reference: 12684 Fix/Workaround: None 5 - Maximum toggle frequency on all pins in worst case operating condition is 8MHz. This affects all operations on the pins, including serial communications. Errata reference: 10335 Fix/Workaround: None. 6 - Do not enable Timers/Counters, AC (Analog Comparator), GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) to control Digital outputs in standby sleep mode.
Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 35.2.4 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset. 2 - The SysTick timer does not generate a wake up signal to the Power Manager, and therefore cannot be used to wake up the CPU from sleep mode. Errata reference: 11012 Fix/Workaround: None. 35.2.
35.2.6 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) 35.2.7 DFLL48M 1 - If the firmware writes to the DFLLMUL.MUL register in the same cycle as the closed loop mode tries to update it, the fine calibration will first be reset to midpoint and then incremented/decremented by the closed loop mode.
o Wait for fine lock (PCLKSR.DFLLLCKF set to 1) o Switch back system clock/module clocks to the DFLL48M Better accuracy is achieved using a high multiplier for the DFLL48M, using a scaled down or slow clock as reference. A multiplier of 6 will have a theoretical worst case frequency deviation from the reference clock of +/- 8.33%. A multiplier of 500 will have a theoretical worst case frequency deviation from the reference clock of +/- 0.1%.
2 - When the SERCOM is in slave SPI mode, the BUFOVF flag is not automatically cleared when CTRLB.RXEN is set to zero. Errata reference: 10563 Fix/Workaround: The BUFOVF flag must be manually cleared by software. 3 - The SERCOM SPI BUFOVF status bit is not set until the next character is received after a buffer overflow, instead of directly after the overflow has occurred. Furthermore the CTRLA.IBON bit will always be zero and cannot be changed. Errata reference: 10551 Fix/Workaround: None. 35.2.
- Configure the cache in LOW_POWER mode by writing 0x1 into the NVMCTRL CTRLB.READMODE bits. 35.3 Revision B 35.3.1 NVMCTRL 1 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988 Fix/Workaround: When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row. 35.
Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 4 - The PORT output driver strength feature is not available. Errata reference: 12684 Fix/Workaround: None 5 - Maximum toggle frequency on all pins in worst case operating condition is 8MHz. This affects all operations on the pins, including serial communications.
10 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 35.3.4 PM 1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference: 12196 Fix/Workaround: A new debug session must be restart after a watchdog reset.
3 - When a GCLK is locked and the generator used by the locked GCLK is not GCLK generator 1, issuing a GCLK software reset will lock up the GCLK with the SYNCBUSY flag always set. Errata reference: 10645 Fix/Workaround: Do not issue a GCLK SWRST or map GCLK generator 1 to ""locked"" GCLKs. 35.3.6 XOSC32K 1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933 Fix/Workaround: Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0) 35.3.
If the application requires on-the-fly DFLL calibration (temperature/VCC drift compensation), the firmware should perform, either periodically or when the DFLL48M frequency differ too much from target frequency (indicated by DFLLVAL.DIFF), the following: o Switch system clock/module clocks to different clock than DFLL48M o Re-initiate a DFLL48M closed loop lock sequence by disabling and re-enabling the DFLL48M o Wait for fine lock (PCLKSR.
Fix/Workaround: The BUFOVF flag must be manually cleared by software. 3 - The SERCOM SPI BUFOVF status bit is not set until the next character is received after a buffer overflow, instead of directly after the overflow has occurred. Furthermore the CTRLA.IBON bit will always be zero and cannot be changed. Errata reference: 10551 Fix/Workaround: None. 35.3.10 ADC 1 - The automatic right shift of the result when accumulating/averaging ADC samples does not work.
- turn off cache before issuing flash commands by setting the NVMCTRL CTRLB.CACHEDIS bit to one. - Configure the cache in LOW_POWER mode by writing 0x1 into the NVMCTRL CTRLB.READMODE bits. 35.
36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev.
z Updated Table 32-1 z Updated IVDD and IGND max values z Added a detailed table note for IVDD and IGND z Added Table 32-2 z Updated Table 32-3 z z Removed table note (1) related to the operating conditions Updated the Table 32-7 z Updated values in ACTIVE and IDLE0/1/2 modes z Updated the max values @ 85°C in STANDBY modes z z z Updated title of Table 32-9 to “RevD and later normal I/O Pins characteristics” z Updated IOL and IOH values in Table 32-9 z Updated title in Table 32-9 z Up
36.2 Rev. J – 12/2013 NVMCTRL - NonVolatile Memory Controller 36.3 Cleaned up the CTRLB register. Rev.
Updated “Clock System” on page 73 z Updated the clock names in the Figure 13-1 z Updated the description of Generic Clock generators and Generic Clocks in the “Clock Distribution” on page 73 z Updated Figure 13-2 z Updated the description of “Read-Synchronization” on page 76 z Changed the title “Enable Write-Synchronization” to “Write-Synchronization of CTRL.
z Updated “Overview” on page 101 z “power save modes” is changed to “sleep modes” z A new line is added: “This is because during STANDBY sleep mode the internal voltage regulator will be in low power mode” z Updated “Features” on page 101 z Updated “Clocks” on page 103 z z z z “This clock” is changed to “The clock source for GCLK_MAIN” Updated “Interrupts” on page 103 z z Clock control: “Generates” is changed to “Controls” Added: “Refer to “Nested Vector Interrupt Controller” on page 25 for
z Updated Table 15-4 z Updated “IDLE Mode” on page 109 z z Power Manager (cont.
z Updated “Additional Features” on page 136 z z Updated “3.3V Brown-Out Detector (BOD33)” on page 137 z z z z SYSCTRL - System Control (cont.
z Updated the description of “Events” on page 240 z Updated “Sleep Mode Operation” on page 244 z EIC - External Interrupt Controller z z Updated “Additional Features” on page 243 z Updated “Power Management” on page 259 z Added: “- refer to CTRLB” Added “Basic Operations” on page 260 z Updated “Interrupts” on page 259 z Updated the description of “NVM Read” on page 262 z Updated “Register Access Protection” on page 259 z Added: “- refer to INTFLAG” and “- refer to STATUS” z Updated the
z Updated “Disclaimer” on page 563.
36.4 Rev. H – 10/2013 Configuration Summary Added 256KB Flash and 32KB SRAM to the SAM D20E Ordering Information Added SAMD20E18 to the “SAM D20E” on page 4 SYSCTRL Added note to INTFLAG NVMCTRL Updated links to the Table 20-3 SERCOM USART Updated Table 24-6. SERCOM PAD[X] renamed PAD[X] ADC z Updated the “Features” on page 474.
z Updated the Table 32-22. Added min and max values for IDD z Replaced VDD by VDDANA in the Table 32-23 z Updated the Table 32-25 z z Added min and max values Added characterization data for VSCALE z Updated the Table 32-18, Table 32-24 and Table 32-27 z Electrical Characteristics Added min and max values z Updated Table 32-30 and Table 32-31.
36.6 Rev. F – 10/2013 I/O Multiplexing and Considerations Updated the Table 5-1 Memories Updated the Table 9-4 z z 36.
DSU Updated the Figure 12-1 z Removed HRAM from the block diagram Updated “Clock System” on page 73 Clock System SYSCTRL NVMCTRL PORT EVSYS z The description of the Basic Read Request has been updated z Updated the Figure 13-3 z Updated the writing of the interrupt sources in “Interrupts” on page 138 z Added the reference to INTFLAG Updated the Figure 20-2 z Removed the blue mark from the figure z “CPU Local Bus” on page 282: IOBUS address 0x60000000 added z Removed RWM from the descripti
z Updated the description of “Multiplexing Signals” z Replaced “PORT controller” by “PORT” z Set the Table 5-1 as a continuing table z Updated the table notes of the Table 5-1 z Replaced I/O lines by I/O pins on the page 17 Signal Description z Removed the column “Comment” from the table Power Supply z Removed “nominal” from power supplies z Updated the description of vector regulator z Added link to the “Schematic Checklist” Pinout Clock System Added the link in the description of “Wr
ADC “Accumulation” on page 481: Section added “Averaging” on page 481: Section updated “Oversampling and Decimation” on page 482: Section updated AC “Starting a Comparison” on page 516: Heading updated from Basic Operation. “Synchronization” on page 523: Updated with list of write-synchronized bits and registers Register property updated to “Write-Synchronized”: SYSCTRL Errata Rev. B Errata Rev. A z CTRLA, Comparator Control n z Removed VDDMON and ENABLE bits from registers.
Appendix A. Conventions A.1 Numerical Notation Table A-1. A.2 A.3 Numerical Notation Symbol Description 165 Decimal number 0b0101 Binary number (example 0b0101 = 5 decimal) 0101 Binary numbers are given without suffix if unambiguous 0x3B24 Hexadecimal number X Represents an unknown or don't care value Z Represents a high-impedance (floating) state for either a signal or a bus Memory Size and Type Table A-2.
Table A-3. A.4 Frequency and Time (Continued) Symbol Description ms millisecond µs microsecond ns nanosecond Registers and Bits Table A-4. Register and Bit Mnemonics Symbol Description R/W Read/Write accessible register bit. The user can read from and write to this bit. R Read-only accessible register bit. The user can only read this bit. Writes will be ignored. W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an undefined value.
Appendix B. Acronyms and Abbreviations Table B-1 contains acronyms and abbreviations used in this document. Table B-1.
Table B-1.
Atmel | SMART SAM D20 [DATASHEET] Atmel-42129K–SAM-D20_datasheet–06/2014 653
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 2.3 SAM D20E . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip-Erase . . . . .
17. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . .
22.2 22.3 22.4 22.5 22.6 22.7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . .
27.4 27.5 27.6 27.7 27.8 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . .
32.7 32.8 32.9 32.10 32.11 32.12 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PTC Typical Characteristics. . . . . . . . . . . . . . . .
ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-42129K-SAM-D20_datasheet_06/2014. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, QTouch®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, Cortex® and others are registered trademarks or trademarks of ARM Ltd.
