Datasheet
938
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 39-19. Synchronized Update of Comparison Values and Configurations
39.6.5.6 Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2, an interrupt can be generated at the end of the
corresponding channel period (CHIDx in the PWM Interrupt Status Register 1 (PWM_ISR1)), after a fault event (FCHIDx
in the PWM_ISR1), after a comparison match (CMPMx in the PWM_ISR2), after a comparison update (CMPUx in the
PWM_ISR2) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and UNRE in the
PWM_ISR2).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read
operation in the PWM_ISR2 occurs.
A channel interrupt is enabled by setting the corresponding bit in PWM_IER1 and PWM_IER2. A channel interrupt is
disabled by setting the corresponding bit in PWM_IDR1 and PWM_IDR2.
39.6.5.7 Register Write Protection
To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by
writing the field WPCMD in the “PWM Write Protection Control Register” (PWM_WPCR). They are divided into six
groups:
Register group 0:
“PWM Clock Register” on page 943
Register group 1:
“PWM Disable Register” on page 945
Register group 2:
“PWM Sync Channels Mode Register” on page 951
“PWM Channel Mode Register” on page 979
“PWM Stepper Motor Mode Register” on page 971
Register group 3:
“PWM Channel Period Register” on page 983
“PWM Channel Period Update Register” on page 984
PWM_CMPVUPDx Value
Comparison Value
for comparison x
User's
Writing
PWM_CMPVx
End of channel0 PWM period and
end of Comparison Update Period
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
PWM_CMPMx
User's
Writing
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written