Datasheet

735
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
35.6.1 UART Control Register
Name: UART_CR
Address: 0x400E0600 (0), 0x400E0800 (1)
Access: Write-only
• RSTRX: Reset Receiver
0: No effect.
1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0: No effect.
1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0: No effect.
1: The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver
is stopped.
• TXEN: Transmitter Enable
0: No effect.
1: The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX
is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME and OVRE in the UART_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –