Datasheet

730
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 35-4. Character Reception
35.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the Receive Holding register (UART_RHR) and the RXRDY
status bit in the Status register (UART_SR) is set. The bit RXRDY is automatically cleared when UART_RHR is read.
Figure 35-5. Receiver Ready
35.5.2.4 Receiver Overrun
The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the Peripheral Data
Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received. OVRE is
cleared when the software writes a 1 to the bit RSTSTA (Reset Status) in UART_CR.
Figure 35-6. Receiver Overrun
35.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in the Mode register (UART_MR). It then compares the result with the received parity bit. If different, the parity error
bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when UART_CR is written with the
bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit
remains at 1.
D0 D1 D2 D3 D4 D5 D6 D7
URXD
True Start Detection
Sampling
Parity Bit
Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
D0 D1 D2 D3 D4 D5 D6 D7 PS
S
D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 PS
S
D0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTSTA
RXRDY
OVRE
stop
stop