Datasheet

721
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0: The clock is not stretched.
1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in Figure 34-28 on page 708 and Figure 34-29 on page 709.
• EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0: A slave access is being performing.
1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 34-30 on page 709 and Figure 34-31 on page 710
• ENDRX: End of RX buffer
0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1: The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer
0: The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1: The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full
0: TWI_RCR or TWI_RNCR have a value other than 0.
1: Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0: TWI_TCR or TWI_TNCR have a value other than 0.
1: Both TWI_TCR and TWI_TNCR have a value of 0.