Datasheet

693
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 34-10. Master Read with Multiple Data Bytes
RXRDY is used as Receive Ready for the PDC receive channel.
34.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.
34.8.6.1 7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write)
accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When
performing read operations with an internal address, the TWI performs a write operation to set the internal address into
the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR)
is sometimes called “repeated start” (Sr) in I
2
C fully-compatible devices. See Figure 34-12. See Figure 34-11 and Figure
34-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0.
Table 34-6 shows the abbreviations used in Figure 34-11 and Figure 34-12.
NA
AS DADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Table 34-6. Abbreviations
Abbreviation Definition
SStart
Sr Repeated Start
PStop
WWrite
R Read
A Acknowledge
NA Not Acknowledge
DADR Device Address
IADR Internal Address