Datasheet

SAM4S Series [DATASHEET]

11100F–ATARM–29-Jan-14

Instruction Prefetch and Branch Prediction

The Cortex-M4 processor:

 Prefetches instructions ahead of execution

 Speculatively prefetches from branch target addresses.

12.4.2.4 Software Ordering of Memory Accesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory

transactions. This is because:

 The processor can reorder some memory accesses to improve efficiency, providing this does not affect the

behavior of the instruction sequence.

 The processor has multiple bus interfaces

 Memory or devices in the memory map have different wait states

 Some memory accesses are buffered or speculative.

“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order

of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier

instructions to force that ordering. The processor provides the following memory barrier instructions:

DMB

The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent

memory transactions. See “DMB” .

DSB

The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before

subsequent instructions execute. See “DSB” .

ISB

The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is

recognizable by subsequent instructions. See “ISB” .

MPU Programming

Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by

subsequent instructions.

12.4.2.5 Bit-banding

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions

occupy the lowest 1 MB of the SRAM and peripheral memory regions.

The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:

 Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6.

 Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 12-

Table 12-6. SRAM Memory Bit-banding Regions

Address Range Memory Region Instruction and Data Accesses

0x20000000–0x200FFFFF SRAM bit-band region

Direct accesses to this memory range behave as SRAM memory accesses,

but this region is also bit-addressable through bit-band alias.

0x22000000–0x23FFFFFF SRAM bit-band alias

Data accesses to this region are remapped to bit-band region. A write

operation is performed as read-modify-write. Instruction accesses are not

remapped.