Datasheet

666
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
asserted systematically during a time “DLYBCS” (the value of the CSNAAT bit is taken into account only if the CSAAT bit
is set to 0 for the same chip select).
Figure 33-11 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
Figure 33-11. Peripheral Deselection
33.7.3.10 Mode Fault Detection
The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI must not
transmit a data. A mode fault is detected when the SPI is programmed in Master mode and a low level is driven by an
A
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
A
DLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
DLYBCT
AA
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 1
NPCS[0..n]
Write SPI_TDR
TDRE
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0