Datasheet

664
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Transfer Size
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer size it has
to point to. The PDC performs the following transfer, depending on the mode and number of bits per data.
 Fixed mode:
 8-bit data:
1-Byte transfer, PDC pointer address = address + 1 byte,
PDC counter = counter - 1
 8-bit to 16-bit data:
2-Byte transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC pointer address = address + 2 bytes,
PDC counter = counter - 1
 Variable mode:
 In Variable mode, PDC pointer address = address +4 bytes and PDC counter = counter - 1 for 8 to 16-bit
transfer size.
 When using the PDC, the TDRE and RDRF flags are handled by the PDC. The user’s application does not
have to check these bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full
(RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral DMA
Controller and user interface, refer to the PDC section of the product datasheet.
33.7.3.7 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 slave peripherals by decoding the four chip select lines, NPCS0 to
NPCS3 with an external decoder/demultiplexer (refer to Figure 33-10). This can be enabled by writing the PCSDEC bit to
1 in SPI_MR.
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven
low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of either
SPI_MR or SPI_TDR (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select registers. As a result, when external decoding is activated, each NPCS chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Consequently, the user has to make
sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 33-10
shows this type of implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not
required for all other chip select lines since mode fault detection is only on NPCS0.