Datasheet

662
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 33-8. PDC Status Register Flags Behavior
33.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the peripheral clock, by a value between 1 and 255.
If the SCBR field is programmed to 1, the operating baud rate is peripheral clock (see the electrical characteristics
section for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field in SPI_CSR.
This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.
33.7.3.4 Transfer Delays
Figure 33-9 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be
programmed to modify the transfer waveforms:
 The delay between the chip selects. It is programmable only once for all chip selects by writing the DLYBCS field in
SPI_MR. The SPI slave device deactivation delay is managed through DLYBCS. If there is only one SPI slave
device connected to the master, the DLYBCS field does not need to be configured. If several slave devices are
connected to a master, DLYBCS must be configured depending on the highest deactivation delay. Refer to the SPI
slave device electrical characteristics.
 The delay before SPCK, independently programmable for each chip select by writing the DLYBS field. The SPI
slave device activation delay is managed through DLYBS. Refer to the SPI slave device electrical characteristics
to define DLYBS.
 The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. The time required by the SPI slave device to process received data is managed through DLYBCT.
This time depends on the SPI slave system activity.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
654321
SPCK
MOSI
(from master)
NPCS0
MSB LSB
654321
12
3
ENDTX
TXEMPTY
MSB
LSB
654321
654321
MISO
(from slave)
654321 654321
ENDRX
TXBUFE
RXBUFF
TDRE
(not required
if PDC is used)
PDC loads first byte
PDC loads 2nd byte
(double buffer effect)
PDC loads last byte
MSB
MSBMSB MSB
LSBLSB
LSB
LSB