Datasheet

588
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
31.7.29 PIO Slow Clock Divider Debouncing Register
Name: PIO_SCDR
Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC)
Access: Read/Write
• DIV: Slow Clock Divider Selection for Debouncing
Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
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–– DIV
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DIV