Datasheet

507
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
9. Enable the peripheral clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via reg-
isters PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.
29.15 Clock Switching Details
29.15.1 Master Clock Switching Timings
Table 29-1 and Table 29-2 give the worst case timings required for the master clock to switch from one selected clock to
another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of
64 clock cycles of the newly selected clock has to be added.
Notes: 1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 29-1. Clock Switching Timings (Worst Case)
Fro
m Main Clock SLCK PLL Clock
To
Main
Clock
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 29-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro
m PLLA Clock PLLB Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK