Datasheet

497
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
28.6 Divider and PLL Block
The device features two divider/two PLL Blocks that permit a wide range of frequencies to be selected on either the
master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to the
embedded USB device port regardless of the frequency of the main clock.
Figure 28-4 shows the block diagram of the dividers and PLL blocks.
Figure 28-4. Dividers and PLL Block Diagram
28.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLLs (PLLA, PLLB) allow multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends
on the respective source signal frequency and on the parameters DIV (DIVA, DIVB) and MUL (MULA, MULB). The factor
applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0 or DIV=0,the PLL is disabled and its
power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field
and DIV higher than 0.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA, LOCKB) bit in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT, PLLBCOUNT) in CKGR_PLLR
(CKGR_PLLAR, CKGR_PLLBR) are loaded in the PLL counter. The PLL counter then decrements at the speed of the
Divider B
DIVB
PLL B
MULB
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK
PLLADIV2
PLLBDIV2
CKGR_PLLBR
CKGR_PLLBR
CKGR_PLLBR
CKGR_PLLAR
CKGR_PLLAR
CKGR_PLLAR
PMC_MCKR
PMC_MCKR
PMC_SR
PMC_SR