Datasheet

475
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
27. Peripheral DMA Controller (PDC)
27.1 Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories. The
link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface
of mono-directional channels (receive-only or transmit-only) contains two 32-bit memory pointers and two 16-bit
counters, one set (pointer, counter) for the current transfer and one set (pointer, counter) for the next transfer. The
bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer,
counter) is used by the current transmit, next transmit, current receive and next receive.
Using the PDC decreases processor overhead by reducing its intervention during the transfer. This lowers significantly
the number of clock cycles required for a data transfer, improving microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When
the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
27.2 Embedded Characteristics
 Performs Transfers to/from APB Communication Serial Peripherals
 Supports Half-duplex and Full-duplex Peripherals