Datasheet

432
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
26.3 I/O Lines Description
26.4 Product Dependencies
26.4.1 I/O Lines
The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC
are not used by the application, they can be used for other purposes by the PIO Controller.
26.4.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SMC clock.
26.5 External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and appears to
be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see
Figure 26-1).
Table 26-1. I/O Line Description
Name Description Type Active Level
NCS[3:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Signal Output Low
A[23:0] Address Bus Output
D[7:0] Data Bus I/O
NWAIT External Wait Signal Input Low
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low