Datasheet

420
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Each algorithm may be complemented by selecting a default master configuration for each slave.
In case of re-arbitration, specific conditions apply. See Section 25.5.1 “Arbitration Rules“.
25.5.1 Arbitration Rules
Each arbiter has the ability to arbitrate between requests of two or more masters. To avoid burst breaking and to provide
the maximum throughput for slave interfaces, arbitration should take place during the following cycles:
1. Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2. Single cycles: When a slave is performing a single access.
3. End of burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined burst length, pre-
dicted end of burst matches the size of the transfer but is managed differently for undefined burst length. See
Section 25.5.1.1 “Undefined Length Burst Arbitration” on page 420“.
4. Slot cycle limit: When the slot cycle counter has reached the limit indicating that the current master access is too
long and must be broken. See Section 25.5.1.2 “Slot Cycle Limit Arbitration” on page 420.
25.5.1.1 Undefined Length Burst Arbitration
In order to prevent slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic to re-
arbitrate before the end of the INCR transfer.
A predicted end of burst is used for defined length burst transfer, which is selected between the following:
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken.
2. Four-beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.
3. Eight-beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.
4. Sixteen-beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR
transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
25.5.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break accesses that are too long, such as very long bursts on a very slow slave
(e.g. an external low-speed memory). At the beginning of the burst access, a counter is loaded with the value previously
written in the SLOT_CYCLE field of the related MATRIX_SCFG and decreased at each clock cycle. When the counter
reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half-word or word transfer.
25.5.2 Round-Robin Arbitration
Bus Matrix arbiters use the round-robin algorithm to dispatch the requests from different masters to the same slave. If
two or more masters make a request at the same time, the master with the lowest number is serviced first. The others are
then serviced in a round-robin manner.
Three round-robin algorithms are implemented:
 Round-Robin arbitration without default master
 Round-Robin arbitration with last access master
 Round-Robin arbitration with fixed default master
25.5.2.1 Round-Robin arbitration without default master
Round-robin arbitration without default master is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix
to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current
access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency
cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant
bursts.