Datasheet

332
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
18.4.6 Supply Controller Wake-up Mode Register
Name: SUPC_WUMR
Address: 0x400E141C
Access: Read/Write
This register is located in the VDDIO domain.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
 SMEN: Supply Monitor Wake-up Enable
0 (NOT_ENABLE): The supply monitor detection has no wake-up effect.
1 (ENABLE): The supply monitor detection forces the wake-up of the core power supply.
 RTTEN: Real-time Timer Wake-up Enable
0 (NOT_ENABLE): The RTT alarm signal has no wake-up effect.
1 (ENABLE): The RTT alarm signal forces the wake-up of the core power supply.
 RTCEN: Real-time Clock Wake-up Enable
0 (NOT_ENABLE): The RTC alarm signal has no wake-up effect.
1 (ENABLE): The RTC alarm signal forces the wake-up of the core power supply.
 LPDBCEN0: Low-power Debouncer Enable WKUP0
0 (NOT_ENABLE): The WKUP0 input pin is not connected with low-power debouncer.
1 (ENABLE): The WKUP0 input pin is connected with low-power debouncer and forces a system wake-up.
 LPDBCEN1: Low-power Debouncer Enable WKUP1
0 (NOT_ENABLE): The WKUP1 input pin is not connected with low-power debouncer.
1 (ENABLE): The WKUP1 input pin is connected with low-power debouncer and forces a system wake-up.
 LPDBCCLR: Low-power Debouncer Clear
0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR
registers.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– LPDBC
15 14 13 12 11 10 9 8
– WKUPDBC ––––
76543210
LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –