Datasheet

325
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 18-6. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors)
The debouncing period duration is configurable. The period is made for all debouncers (i.e., the duration cannot be
adjusted separately for each debouncer). The number of successive identical samples to wake up the system can be
configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time between two samples can be
configured by programming the TPERIOD field in the RTC_MR. Power parameters can be adjusted by modifying the
period of time in the THIGH field in RTC_MR.
The wake-up polarity of the inputs can be independently configured by writing WKUPT0 and/ or WKUPT1 fields in
SUPC_WUMR.
In order to determine which wake-up/tamper pin triggers the system wake-up, a status flag is associated for each low-
power debouncer. These flags are read in SUPC_SR.
A debounce event (tamper detection) can perform an immediate clear (0 delay) on the first half the general-purpose
backup registers (GPBR). The LPDBCCLR bit must be set in SUPC_MR.
Note that it is not mandatory to use the RTCOUTx pin when using the WKUP0/WKUP1 pins as tampering inputs in any
mode. Using the RTCOUTx pin provides a “sampling mode” to further reduce the power consumption of the tamper
detection circuitry. If RTCOUTx is not used, the RTC must be configured to create an internal sampling point for the
debouncer logic. The period of time between two samples can be configured by programming the TPERIOD field in
RTC_MR.
Figure 18-7 illustrates the use of WKUPx without the RTCOUTx pin.
MCU
WKUP0
WKUP1
RTCOUTx
Pull-down
Resistors
GND GND
GND