Datasheet

322
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 18-3. Raising the VDDIO Power Supply
18.3.6 Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in Section 18.3.5
”Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core power
supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
 a supply monitor detection
 a brownout detection
18.3.6.1 Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This is enabled by setting the SMRSTEN bit in
SUPC_SMMR.
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a
minimum of 1 slow clock cycle.
18.3.6.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is
operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled,
the Supply Controller asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR.
Zero-Power Power-On
Reset Cell output
22 - 42 kHz RC
Oscillator output
Fast RC
Oscillator output
Backup Power Supply
vr_on
bodcore_in
vddcore_nreset
NRST
(no ext. drive assumed)
proc_nreset
Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.
periph_nreset
7 x Slow Clock Cycles
3 x Slow Clock
Cycles
2 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
TON Voltage
Regulator
Zero-Power POR
Core Power Supply
RSTC.ERSTL
(5 for startup slow RC + 2 for synchro.)
default = 2