Datasheet

319
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
18.3 Supply Controller Functional Description
18.3.1 Supply Controller Overview
The device is divided into two power supply areas:
 The backup VDDIO power supply that includes the Supply Controller, a part of the Reset Controller, the slow clock
switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer
and the Real-time Clock.
 The core power supply that includes the other part of the Reset Controller, the Brownout Detector, the processor,
the SRAM memory, the Flash memory and the peripherals.
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when the
VDDIO power supply rises (when the system is starting) or when the backup low-power mode is entered.
The SUPC also integrates the slow clock generator which is based on a 32 kHz crystal oscillator and an embedded 32
kHz RC oscillator. The slow clock defaults to the RC oscillator, but the software can enable the crystal oscillator and
select it as the slow clock source.
The Supply Controller and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell.
The zero-power power-on reset allows the SUPC to start properly as soon as the VDDIO voltage becomes valid.
At start-up of the system, once the backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is stabilized,
the SUPC starts up the core by sequentially enabling the internal voltage regulator. The SUPC waits until the core
voltage VDDCORE is valid, then releases the reset signal of the core “vddcore_nreset” signal.
Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply monitor
detects a voltage level on VDDIO that is too low, the SUPC asserts the reset signal of the core “vddcore_nreset” signal
until VDDIO is valid. Likewise, if the brownout detector detects a core voltage level VDDCORE that is too low, the SUPC
asserts the reset signal “vddcore_nreset” until VDDCORE is valid.
When the backup low-power mode is entered, the SUPC sequentially asserts the reset signal of the core power supply
“vddcore_nreset” and disables the voltage regulator, in order to supply only the VDDIO power supply. Current
consumption is reduced to a few microamps for the backup part retention. Exit from this mode is possible on multiple
wake-up sources including an event on WKUP pins, or a clock alarm. To exit this mode, the SUPC operates in the same
way as system start-up.