Datasheet

203
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
12.9.1.3 Interrupt Control and State Register
Name: SCB_ICSR
Access: Read/Write
Reset: 0x000000000
The SCB_ICSR provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clear-pending
bits for the PendSV and SysTick exceptions.
It indicates:
• The exception number of the exception being processed, and whether there are preempted active exceptions,
• The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a write of
1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal
is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing a 1 to this bit is the only way to set the PendSV exception state to pending.
• PENDSVCLR: PendSV Clear-pending
31 30 29 28 27 26 25 24
NMIPENDSET – PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR –
23 22 21 20 19 18 17 16
– ISRPENDING VECTPENDING
15 14 13 12 11 10 9 8
VECTPENDING RETTOBASE – VECTACTIVE
76543210
VECTACTIVE