Datasheet

1190
SAM4S Series [DATASHEET]
11100F–ATARM–22-Nov-13
CMCC
Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register”
and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in
Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description completed.
“0xXX - 0xFC” offset replaced with “0x38 - 0xFC” in the last row in Table 22-1, “Register Mapping”. In Figure
22-1, replaced “Cortex MPPB” with “APB Interface” in Block Diagram.
8373
rfo
CRCCU
TRWIDTH bitfield description table completed in Section 23.6.2 “Transfer Control Register”.
Updated Section 23.1 “Description” and Section 23.5.2 “CRC Calculation Unit Operation”.
8303
rfo
PDC
Offset data for Register Mapping updated in Table 27-2, “Register Mapping”.
“ABP bridge” changed to “APB bridge” in Section 27.1 “Description”.
7976
rfo
PMC
Section 28.1.5.5 “Software Sequence to Detect the Presence of Fast Crystal” added.
Updated CKGR_MOR register reset value to 0x0000_0008 in Section 28.2.16 “Power Management Controller
(PMC) User Interface”.
8371
8448
CHIPID
Section 29.3.1 “Chip ID Register”, in ARCH bitfield description table, rows sharing SAM3/SAM4 names
reconfigured with standalone rows for each name.
Section 29.3.1 “Chip ID Register”, in ARCH bitfield description table, various devices added or removed.
Section 29.3.1 “Chip ID Register”, in SRAMSIZ bitfield description table, replaced 1K/1Kbyte with
192K/192Kbyte for value1.
In Section 29.2 “Embedded Characteristics”, updated Table 29-1, “ATSAM4S Chip IDs Registers”.
7730
7977,
8034, 8383
8036
rfo
PIO
DSIZE bit description updated in Section 30.7.49 “PIO Parallel Capture Mode Register”.
Section 30.4.2 “External Interrupt Lines” added. Section 30.4.4 “Interrupt Generation” updated.
7705
rfo
SSC
Removed Table 30-4 in Section 31.7.1.1 “Clock Divider”.
Last line (PDC register) updated in Table 31-5, “Register Mapping”.
Reworked tables and bitfield descriptions in Section 31.9.3 “SSC Receive Clock Mode Register”, Section
31.9.4 “SSC Receive Frame Mode Register”, Section 31.9.5 “SSC Transmit Clock Mode Register”, Section
31.9.6 “SSC Transmit Frame Mode Register”.
7303
7971
8466
SPI
In
Section
32.2 “Embedded Characteristics”, added the 2 first bullets, deleted the previous last bullet. 8544
Table 48-4. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continued)
Doc. Rev.
11100C Comments
Change
Request
Ref.