Datasheet

1184
SAM4S Series [DATASHEET]
11100F–ATARM–22-Nov-13
Section 33. “Serial Peripheral Interface (SPI)”
‘MCK’ replaced with ‘peripheral clock’ throughout.
Updated Figure 33-1 ”Block Diagram”, Figure 33-3 ”SPI Transfer Format (NCPHA = 1, 8 bits per transfer)” and
Figure 33-4 ”SPI Transfer Format (NCPHA = 0, 8 bits per transfer)”
Modified Section 33.7.3 “Master Mode Operations”,
Modified Section 33.7.5 “Register Write Protection”, Section 33.8.10 “SPI Write Protection Mode Register” and
Section 33.8.11 “SPI Write Protection Status Register”
MCK replaced with peripheral clock
Section 34. “Two-wire Interface (TWI)”
Section 34.2 “Embedded Characteristics”; removed bullet “Next Buffer Support”
Added details on master/slave mode configuration in Step 2 and fixed typos (‘TXDIS’ --> ‘TXTDIS’, ‘RXDIS’ -->
‘RXTDIS’), added commands 6-9 in Section 34.8.7.1 “Data Transmit with the PDC” and and commands 4 and 12 in
Section 34.8.7.2 “Data Receive with the PDC”.
Updated Figure 34-27 ”Master Performs a General Call”.
Corrected TWI_THR to Write-only access in Table 34-7, “Register Mapping” and Section 34.11.11 “TWI Transmit
Holding Register”
Added Section 34.10.6 “Using the Peripheral DMA Controller (PDC) in Slave Mode”
Section 34.11.6 “TWI Status Register”, updated the description of “NACK: Not Acknowledged (clear on read)” ,
used in master mode
Section 35. “Universal Asynchronous Receiver Transmitter (UART)”
Corrected the offset for PDC registers in Section 35.6 “Universal Asynchronous Receiver Transmitter (UART) User
Interface”.
Section 36. “Universal Synchronous Asynchronous Receiver Transceiver (USART)”
Table 36-2, “I/O Line Description”: corrected RXD type from Input to I/O.
Added a paragraph on IRDA_FILTER programming criteria in Section 36.7.5.3 “IrDA Demodulator” and in the
corresponding bitfield description in Section 36.8.20, “USART IrDA FILTER Register”.
Corrected
Figure 36-22, “Parity Error” for stop bit value.
Replaced 33400 baudrate with 38400 in Table 36-10, “Maximum Timeguard Length Depending on Baud Rate,” on
page 765, Table 36-11, “Maximum Time-out Period,” on page 766.
Section 36.7.10 “Register Write Protection”: Changed section title and re-worked content. Section 36.8.22 “USART
Write Protection Mode Register” and Section 36.8.23 “USART Write Protection Status Register”: Changed register
names and modified bit and field descriptions.
In Section 36.7.3.4 “Manchester Decoder”, updated information on RXIDLEV bit in 4th paragraph.
Section 36.8.3 “USART Mode Register”: in table describing ‘PAR Parity Type’ field, added value ‘5’ and description.
Section 36.8.18 “USART FI DI RATIO Register”: modified FI_DI_RATIO field from 16 bits to 11 bits.
In Section 36.8.21 “USART Manchester Configuration Register” added RXIDLEV as bit 31 and added bit description.
Section 37. “Timer Counter (TC)”
TIOA1 replaced with TIOB1 in Section 37.1 “Description” and added a note for ENETRG description in Section
37.7.3 “TC Channel Mode Register: Waveform Mode”.
Erroneous description of TCCLKS table, rows 0 to 4 reworked in Section 37.7.2 “TC Channel Mode Register:
Capture Mode” and Section 37.7.3 “TC Channel Mode Register: Waveform Mode”
Section 37.7.14 “TC Block Mode Register”: corrected TC2XC2S field configuration values: value 2 is TIOA0 (was
TIOA1); value 3 is TIOA1 (was TIOA2)
Section 7.2 “16-bit Counter”, Section 7.12.1 “WAVSEL = 00”, Figure 37-9 “WAVSEL = 10 without Trigger”, Figure 37-
10 “WAVSEL = 10 with Trigger”, Section 37.6.11.3 “WAVSEL = 01”, and Figure 37-14 “WAVSEL = 11 with Trigger”:
replaced “0xFFFF” with “
2
n
-1” in first paragraph (with “n” representing counter size)
Table 48-1. SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued)
Doc. Date Changes