Datasheet

1138
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Low Voltage Supply
The ADC performs in 10-bit mode or in 12-bit mode. Working at low voltage (VDDIN or/and V
ADVREF
) between 2 and 2.4V
is subject to the following restrictions:
 The field IBCTL must be 00 to reduce the biasing of the ADC under low voltage. See Section 44.8.1.1 “ADC Bias
Current”.
 In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz).
 In 12-bit mode, the ADC clock should not exceed 2 MHz (max signal bandwidth is 100 kHz).
44.8.5.3 ADC Channel Input Impedance
Figure 44-16. Input Channel Model
where:
 Z
IN
is input impedance in single-ended or differential mode
 C
IN
= 1 to 8 pF +/-20% depending on the gain value and mode (SE or DIFF); temperature dependency is negligible
 R
ON
is typical 2 kΩ and 8 kΩ max (worst case process and high temperature)
 R
ON
is negligible regarding the value of Z
IN
The following formula is used to calculate input impedance:
where:
 f
S
is the sampling frequency of the ADC channel
 Typ values are used to compute ADC input impedance Z
IN
Note: 1. N/A: Not applicable
Table 44-51. Input Capacitance Values
Gain Selection Single-ended Differential
0.5 N/A
(1)
2 pF
1 2 pF 4 pF
2 2 pF 8 pF
44 pFN/A
Single-ended Model Differential Model
R
ON
R
ON
C
IN
C
IN
Z
IN
Z
IN
gnd
Z
IN
1
f
S
C
IN
×
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=