Datasheet

1091
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
43.7.4 DACC Channel Disable Register
Name: DACC_CHDR
Address: 0x4003C014
Access: Write-only
This register can only be written if the WPEN bit is cleared in DACC Write Protection Mode Register.
• CHx: Channel x Disable
0: No effect.
1: Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion, or disabled then re-enabled during a conversion, the
associated analog value and the corresponding EOC flags in DACC_ISR are unpredictable.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
––––––CH1CH0