Datasheet

1052
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
42.6.10 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register
(ADC_MR).
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel
selections. This time has to be programmed through the TRACKTIM field in the ADC_MR.
When the gain, offset or differential input parameters of the analog cell change between two channels, the analog cell
may need a specific settling time before starting the tracking phase. In that case, the controller automatically waits during
the settling time defined in the ADC_MR. Obviously, if the ANACH option is not set, this time is unused.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to
program a precise value in the TRACKTIM field. See the product “ADC Characteristics” section.
42.6.11 Automatic Calibration
The ADC features an automatic calibration (AUTOCALIB) mode for gain errors (calibration).
The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of the ADC Control
Register. The automatic calibration sequence requires a software reset command (SWRST in the ADC_CR) prior to write
AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in the interrupt status register (ADC_ISR), and
an interrupt is generated if EOCAL interrupt has been enabled (ADC_IER).
The calibration sequence will perform an automatic calibration on all enabled channels. The channels required for
conversion do not need to be all enabled during the calibration process if they are programmed with the same gain. Only
channels with different gain settings need to be enabled. The gain settings of all enabled channels must be set before
starting the AUTOCALIB sequence. If the gain settings (ADC_CGR and ADC_COR) for a given channel are changed,
the AUTOCALIB sequence must then be started again.
The calibration data (on one or more enabled channels) is stored in the internal ADC memory.
Then, when a new conversion is started (on one or more enabled channels), the converted value (in ADC_LCDR or
ADC_CDRx) is a calibrated value.
Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain has been already calibrated,
and a new channel with the same settings is enabled after the initial calibration, there is no need to restart a calibration. If
different enabled channels have different gain settings, the corresponding channels must be enabled before starting the
calibration.
If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from Backup mode), the
calibration data in the ADC memory is lost.
Changing the ADC running mode (in ADC_CR) does not affect the calibration data.
Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time, gain error after calibration, refer to the 12-bit ADC electrical characteristics section of the product.
42.6.12 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR. The same structure of data is
repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on user mode of operation (ADC_MR,
ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data read to PDC buffer, carried on a half-word
(16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR, the four most significant bits are
carrying the channel number thus allowing an easier post-processing in the PDC buffer or better checking the PDC buffer
integrity.
42.6.13 Fault Output
The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted according
to the configuration of ADC_EMR (Extended Mode Register) and ADC_CWR (Compare Window Register) and
converted values. When the Compare occurs, the ADC fault output generates a pulse of one Master Clock Cycle to the