Datasheet

101
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
;bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1
to
;
a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
12.6.4.3 LDR and STR, Register Offset
Load and Store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #n is an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register
Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be
signed or unsigned. See “Address Alignment” .
Restrictions
In these instructions:
 Rn must not be PC
 Rm must not be SP and must not be PC