ARM-based Flash MCU SAM4S Series DATASHEET Description The Atmel SAM4S series is a member of a family of Flash microcontrollers based on the high-performance 32-bit ARM ® Cortex ® -M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional dual-bank implementation and cache memory, and up to 160 Kbytes of SRAM.
Features Core ARM Cortex-M4 with 2 Kbytes of cache running at up to 120 MHz Memory Protection Unit (MPU) DSP Instruction Set Thumb®-2 instruction set Pin-to-pin compatible with SAM3N, SAM3S, SAM4N and SAM7S legacy products (64-pin version) Memories Up to 2048 Kbytes embedded Flash with optional dual-bank and cache memory Up to 160 Kbytes embedded SRAM 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines 8-bit Static Memory Controlle
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) for data integrity check of off-/on-chip memories Register write protection I/O Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode Packages 100-lead packages LQFP, 14 x 14 mm, pitch 0.5 mm TFBGA, 9 x 9 mm, pitch 0.
1. Configuration Summary The SAM4S series devices differ in memory size, package and features. Table 1-1 and Table 1-2 summarize the configurations of the device family. Table 1-1.
2. Block Diagram T U O IO D D TST VD VD TD TD I O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-1.
TST PLLA PLLB Power Management Controller U O JTAG and Serial Wire RC OSC 4/8/12MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3-20 MHz Oscillator XOUT Supply Controller WKUP[15:0] DSP MPU 32K OSC I S 32K RC ERASE Power-on Reset 8 General-purpose Backup Registers Real-time Clock Real-time Timer Reset Controller Watchdog Timer Supply Monitor Flash Unique Identifier D CMCC (2 Kb Cache) M NRST 24-bit SysTick Counter NVIC Tamper Detection XIN32 XOUT32 RTCOUT0 RTCOU
T U O IO D D TST VD VD TD TD I O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-3.
TST U O D VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-4.
TST U O D VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-5.
TST D VD VD D O IO U T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-6.
TST U O D VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-7.
3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.62V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.2V Output VDDPLL Oscillator and PLL Power Supply Power 1.
Table 3-1.
Table 3-1.
Table 3-1.
4. Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 48-, 64- and 100-pin versions, SAM4N and SAM7S legacy products in 64-pin versions. 4.1 100-lead Packages and Pinouts Refer to Table 1-1 "Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices" and Table 1-2 "Configuration Summary for SAM4S8/S4/S2 Devices" for the overview of devices available in 100-lead packages. 4.1.1 100-lead LQFP Package Outline Figure 4-1.
4.1.3 100-ball VFBGA Package Outline Figure 4-3.
4.1.4 100-lead LQFP Pinout Table 4-1.
4.1.5 100-ball TFBGA Pinout Table 4-2.
4.1.6 100-ball VFBGA Pinout Table 4-3.
4.2 64-lead Packages and Pinouts Refer to Table 1-1 "Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices" and Table 1-2 "Configuration Summary for SAM4S8/S4/S2 Devices" for the overview of devices available in 64-lead packages. 4.2.1 64-lead LQFP Package Outline Figure 4-4. Orientation of the 64-lead LQFP Package 33 48 49 32 64 17 16 1 4.2.2 64-lead QFN Package Outline Figure 4-5.
4.2.3 64-ball WLCSP Package Outline Figure 4-6. Orientation of the 64-ball WLCSP Package 4.2.4 64-lead LQFP and QFN Pinout Table 4-4.
4.2.5 64-ball WLCSP Pinout Table 4-5.
4.3 48-lead Packages and Pinouts Refer to Table 1-1 "Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices" for the overview of devices available in 48-lead packages. 4.3.1 48-lead LQFP Package Outline Figure 4-7. Orientation of the 48-lead LQFP Package 4.3.2 48-lead QFN Package Outline Figure 4-8.
4.3.3 48-lead LQFP and QFN Pinout Table 4-7.
5. Power Considerations 5.1 Power Supplies The SAM4S has several types of power supply pins: 5.2 VDDCORE pins: Power the core, the first flash rail and the embedded memories and peripherals. Voltage ranges from 1.08V to 1.32V. VDDIO pins: Power the peripheral I/O lines (input/output buffers), the second Flash rail, USB transceiver, backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V–3.6V) USB Transceivers. Can be the same supply ADC, DAC Analog Comp. VDDIN ADC, DAC, Analog Comparator Supply (2.4V–3.6V) VDDOUT Voltage Regulator VDDCORE VDDCORE Supply (1.08V–1.32V) VDDPLL Note: Restrictions: For USB, VDDIO needs to be greater than 3.0V. For ADC and DAC, VDDIN needs to be greater than 2.4V. Figure 5-3 below provides an example of the powering scheme when using a backup battery.
5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The Power Management Controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low-power Modes The SAM4S has the following low-power modes: backup mode, wait mode and sleep mode.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered by setting the WAITMODE bit to 1 in the CKGR_MOR register in conjunction with FLPM = 0 or FLPM = 1 bits of the PMC_FSMR register or by the WFE instruction. The Cortex-M4 is able to handle external or internal events in order to wake-up the core.
5.5.4 Low-power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low-power modes. Table 5-1.
5.6 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. 5.7 Fast Start-up The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start-up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + USB + RTC + RTT).
6.2 System I/O Lines System I/O lines are pins used by oscillators, test mode, reset and JTAG. Table 6-1 provides the SAM4S system I/O lines shared with PIO lines. These pins are software configurable as general-purpose I/O or system pins. At startup, the default function of these pins is always used.
Table 6-1. System I/O Configuration Pin List. SYSTEM_IO bit number Default function after reset Other function Constraints for normal start Configuration (1) 12 ERASE PB12 Low Level at startup 10 DDM PB10 - 11 DDP PB11 - In Matrix User Interface Registers 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - (Refer to the System I/O Configuration Register in the “Bus Matrix” section of the datasheet.
6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length.
7. Product Mapping Figure 7-1.
8. Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The SAM4SD32 device (2x1024 Kbytes) embeds a total of 160 Kbytes of high-speed SRAM. The SAM4SD16 device (2x512Kbytes)embeds a total of 160 Kbytes of high-speed SRAM. The SAM4SA16 device (1024 Kbytes) embeds a total of 160 Kbytes of high-speed SRAM. The SAM4S16 device (1024 Kbytes) embeds a total of 128 Kbytes of high-speed SRAM. The SAM4S8 device (512 Kbytes) embeds a total of 128 Kbytes of high-speed SRAM.
Figure 8-1. Global Flash Organization Sector size Sector name 8 KBytes Small Sector 0 8 KBytes Small Sector 1 48 KBytes Larger Sector 64 KBytes Sector 1 64 KBytes Sector n Sector 0 Each sector is organized in pages of 512 bytes.
Figure 8-2.
Figure 8-3. Flash Size Flash 1 MBytes Flash 512 KBytes Flash 256 KBytes 2 * 8 KBytes 2 * 8 KBytes 2 * 8 KBytes 1 * 48 KBytes 1 * 48 KBytes 1 * 48 KBytes 3 * 64 KBytes 7 * 64 KBytes 15 * 64 KBytes Erasing the memory can be performed as follows: Note: Note: Note: On a 512-byte page inside a sector of 8Kbytes EWP and EWPL commands can be only used in 8-Kbyte sectors.
Table 8-1. Lock Bit Number Product Number of Lock Bits Lock Region Size SAM4S8 64 8 Kbytes SAM4S4 32 8 Kbytes SAM4S2 16 8 Kbytes If a locked region erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.
8.1.3.11 GPNVM Bits The SAM4S16/S8/S4/S2 features two GPNVM bits. These bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC user interface. The SAM4SA16/SD32/SD16 features three GPNVM bits (GPNVM from Flash0) that can be cleared or set respectively through the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC0 User Interface. The GPNVM bits of the SAM4SA16/SD16/SD32 are only available on Flash0. There is no GPNVM bit on Flash1.
9. Real Time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 9.1 Embedded Characteristics Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC or DACC, for example, to start measurement/conversion without processor intervention.
9.2 Real Time Event Mapping List Table 9-1. Real Time Event Mapping List Event Generator Event Manager Function IO (WKUP0/1) General Purpose Backup Register (GPBR) Security / Immediate GPBR clear (asynchronous) on Tamper detection through WKUP0/1 IO pins.
10. System Controller The System Controller is a set of peripherals which allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... 10.1 System Controller and Peripheral Mapping Refer to Figure 7-1, "SAM4S Product Mapping". All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.
11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 11-1.
Table 11-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control 31 PWM X X Pulse Width Modulation 32 CRCCU X X CRC Calculation Unit 33 ACC X X Analog Comparator 34 UDP X X USB Device Port 11.
11.2.1 PIO Controller A Multiplexing Table 11-2.
11.2.2 PIO Controller B Multiplexing Table 11-3.
11.2.3 PIO Controller C Multiplexing Table 11-4.
12. ARM Cortex-M4 Processor 12.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
12.
12.4 Cortex-M4 Models 12.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 12.4.1.1 Processor Modes and Privilege Levels for Software Execution The processor modes are: Thread mode Used to execute application software. The processor enters the Thread mode when it comes out of reset.
12.4.1.3 Core Registers Figure 12-2. Processor Core Registers R0 R1 R2 Low registers R3 R4 R5 General-purpose registers R6 R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Table 12-2.
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ. 2. An entry of Either means privileged and unprivileged software can access the register. 12.4.1.4 General-purpose Registers R0–R12 are 32-bit general-purpose registers for data operations. 12.4.1.5 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This is the reset value.
12.4.1.8 Program Status Register Name: PSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 29 C 28 V 27 Q 26 23 22 21 20 25 24 T 19 18 17 16 12 11 10 9 – 8 ISR_NUMBER 4 3 2 1 0 ICI/IT – 15 14 13 ICI/IT 7 6 5 ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR.
12.4.1.9 Application Program Status Register Name: APSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 23 22 29 C 28 V 27 Q 26 21 20 19 18 – 15 14 25 – 24 17 16 GE[3:0] 13 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than.
12.4.1.10 Interrupt Program Status Register Name: IPSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 – 23 22 21 20 – 15 14 13 12 – 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
12.4.1.11 Execution Program Status Register Name: EPSR Access: Read/Write Reset: 0x000000000 31 23 30 22 29 – 28 21 20 27 26 25 24 T ICI/IT 19 18 17 16 11 10 9 8 – 15 14 13 12 ICI/IT 7 6 5 – 4 3 2 1 0 – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the InterruptibleContinuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
12.4.1.13 Priority Mask Register Name: PRIMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRIMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The PRIMASK register prevents the activation of all exceptions with a configurable priority. • PRIMASK 0: No effect 1: Prevents the activation of all exceptions with a configurable priority.
12.4.1.14 Fault Mask Register Name: FAULTMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FAULTMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI.
12.4.1.15 Base Priority Mask Register Name: BASEPRI Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
12.4.1.16 Control Register Name: CONTROL Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 – 1 SPSEL 0 nPRIV – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread mode. • SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer. 1: PSP is the current stack pointer.
12.4.1.17 Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” for more information. The NVIC registers control interrupt handling.
12.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. Figure 12-3. Memory Map 0xFFFFFFFF Vendor-specific 511 MB memory Private peripheral 1.0 MB bus External device 0xE0100000 0xE00FFFFF 0xE000 0000 0x DFFFFFFF 1.0 GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.
12.4.2.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. Memory Types Normal The processor can re-order transactions for efficiency, or perform speculative reads.
12.4.2.3 Behavior of Memory Accesses The following table describes the behavior of accesses to each region in the memory map. Table 12-4. Memory Access Behavior Address Range Memory Region Memory Type XN 0x00000000–0x1FFFFFFF Code Normal(1) – Executable region for program code. Data can also be put here. 0x20000000–0x3FFFFFFF SRAM Normal (1) – Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas, see Table 12-6.
Instruction Prefetch and Branch Prediction The Cortex-M4 processor: 12.4.2.4 Prefetches instructions ahead of execution Speculatively prefetches from branch target addresses. Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.
Table 12-7. Peripheral Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x40000000–0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit-addressable through bit-band alias. 0x42000000–0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted.
Figure 12-4.
Figure 12-5. Little-endian Format Memory 7 Register 0 31 12.4.2.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
It executes a CLREX instruction It executes a Store-Exclusive instruction, regardless of whether the write succeeds. An exception occurs. This means that the processor can resolve semaphore conflicts between different threads.
Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. Non Maskable Interrupt (NMI) A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software.
Table 12-9.
12.4.3.4 Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 12-6 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. Figure 12-6. Vector Table Exception number IRQ number 255 239 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Vector Offset IRQ239 0x03FC . . . 0x004C . . .
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs.
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means that the exception has more priority than any limits set by the mask registers, see “Exception Mask Registers” .
If another higher priority exception occurs during the exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.
12.4.3.8 Fault Handling Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault: A bus error on: An instruction fetch or vector table load A data access An internally-detected error such as an undefined instruction An attempt to execute an instruction from a memory region marked as Non-Executable (XN). A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” . The software can disable the execution of the handlers for these faults, see “System Handler Control and State Register” . Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in “Exception Model” .
12.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption: Sleep mode stops the processor clock Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” . This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 12.5.
12.5.2.3 External Event Input The processor provides an external event input signal. Peripherals can drive this signal, either to wake the processor from WFE, or to set the internal WFE event register to 1 to indicate that the processor must not enter sleep mode on a later WFE instruction. See “Wait for Event” for more information. 12.5.3 Power Management Programming Hints ISO/IEC C cannot directly generate the WFI and WFE instructions.
12.6 Cortex-M4 Instruction Set 12.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions. Angle brackets, <>, enclose alternative forms of the operand Braces, {}, enclose optional operands The Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13.
Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags VCVT.S32.F32 Sd, Sm Convert between floating-point and integer – VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point – VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding – VCVT.F32.F16 Sd, Sm Converts half-precision value to single-precision – VCVTT.F32.F16 Sd, Sm Converts single-precision register to half-precision – VDIV.
12.6.2 CMSIS Functions ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 12-14.
12.6.3 Instruction Descriptions 12.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” . 12.6.3.
LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction.
If n is 32 or more, then all the bits in the result are cleared to 0. If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 12-9. LSR #3 &DUU\ )ODJ LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10.
RRX Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of the result. See Figure 12-12. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 12-12. RRX &DUU\ )ODJ 12.6.3.
Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags.
Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 12-16.
BCS.W label ; ; ADDS.
12.6.4 Memory Access Instructions The table below shows the memory access instructions. Table 12-17.
12.6.4.1 ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. label is a PC-relative expression. See “PC-relative Expressions” . Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative.
12.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Pre-indexed Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! Post-indexed Addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn.
Examples 12.6.4.3 LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095.
Rt can be SP only for word loads and word stores Rt can be PC only for word loads. When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags.
12.6.4.4 LDR and STR, Unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
12.6.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rt2 is the second register to load or store.
When Rt is PC in a word load instruction: Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples 12.6.4.
register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
12.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution” . reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based.
CMPEQ BNE .... 12.6.4.9 R0, #0 try ; Did this succeed? ; No – try again ; Yes – we have the lock CLREX Clear Exclusive. Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write a 1 to its destination register and fail to perform the store.
12.6.5 General Data Processing Instructions The table below shows the data processing instructions. Table 12-20.
Table 12-20.
12.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: The user must not specify the S suffix The second operand must be a constant in the range 0 to 4095. Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned.
cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.
Examples AND ORREQ ANDS EORS BIC ORN ORNS 12.6.5.3 R9, R2, #0xFF00 R2, R0, R5 R9, R8, #0x19 R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 R7, R11, R14, ASR #32 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right.
These instructions update the N and Z flags according to the result The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” . Examples ASR SLS LSR ROR RRX 12.6.5.4 R7, R1, R4, R4, R4, R8, R2, R5, R5, R5 #9 #3 #6 R6 ; ; ; ; ; Arithmetic shift right by 9 bits Logical shift left by 3 bits with flag update Logical shift right by 6 bits Rotate right by the value in the bottom byte of R6 Rotate right with extend. CLZ Count Leading Zeros.
12.6.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register.
12.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options imm16 is any value in the range 0–65535.
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand” Do not affect the V flag. Examples MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated MOVS R10, R12 ; Write value in R12 to R10, flags get updated MOV R3, #23 ; Write value of 23 to R3 MOV R8, SP ; Write value of stack pointer to R8 MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) ; to the R2 and update flags.
Rd is the destination register. Rn is the register holding the operand. Operation Use these instructions to change endianness of data: REV converts either: 32-bit big-endian data into little-endian data 32-bit little-endian data into big-endian data. REV16 converts either: 16-bit big-endian data into little-endian data 16-bit little-endian data into big-endian data.
12.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SADD16 Performs two 16-bit signed integer additions. SADD8 Performs four 8-bit signed integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand.
12.6.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHADD16 Signed Halving Add 16. SHADD8 Signed Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register.
12.6.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is any of: SHASX Add and Subtract with Exchange and Halving. SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SHASX instruction: 1.
Examples SHASX R7, R4, R2 SHSAX R0, R3, R5 ; ; ; ; ; ; ; ; Adds top halfword of R4 to bottom halfword of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4 and writes halved result to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0. 12.6.5.
12.6.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SSUB16 Performs two 16-bit signed integer subtractions. SSUB8 Performs four 8-bit signed integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to change endianness of data: The SSUB16 instruction: 1.
12.6.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op is any of: SASX Signed Add and Subtract with Exchange. SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SASX instruction: 1.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the ANDS instruction, except that it discards the result.
The UADD16 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Writes the unsigned result in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags.
12.6.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UASX Add and Subtract with Exchange. USAX Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UASX instruction: 1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
Rd is the destination register. Rn is the register holding the first operand. Rm is the register holding the second operand. Operation Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the destination register: The UHADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Shuffles the halfword result by one bit to the right, halving the data. 3.
6. Writes the halfword result of the division in the bottom halfword of the destination register. The UHSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Shifts the result by one bit to the right causing a divide by two, or halving. 3. Writes the halfword result of the subtraction in the top halfword of the destination register. 4. Adds the bottom halfword of the first operand with the top halfword of the second operand. 5.
12.6.5.20 UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHSUB16 Performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
Rm is the second register holding the operand. Operation The SEL instruction: 1. Reads the value of each bit of APSR.GE. 2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second operand register. Restrictions None. Condition Flags These instructions do not change the flags. Examples SADD16 R0, R1, R2 SEL R0, R0, R3 ; Set GE bits based on result ; Select bytes from R0 or R3, based on GE.
12.6.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation The USAD8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the absolute values of the differences together. 3.
12.6.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Ra is the register that contains the accumulation value. Operation The USADA8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2.
12.6.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where op is any of: USUB16 Unsigned Subtract 16. USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The USUB16 instruction: 1.
12.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions. Table 12-21.
12.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional Execution” . S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” .
UMLAL Unsigned Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold the accumulating value. Rn, Rm are registers holding the first and second operands. Operation These instructions interpret the values from Rn and Rm as unsigned 32-bit integers. The UMULL instruction: Multiplies the two unsigned integers in the first and second operands.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used SMLAW Signed Multiply Accumulate (word by halfword). Y specifies which half of the source register Rm is used as the second multiply operand. If Y is T, then the top halfword, bits [31:16] of Rm is used. If Y is B, then the bottom halfword, bits [15:0] of Rm is used. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register.
12.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra ; where: op is one of: SMLAD Signed Multiply Accumulate Dual. SMLADX Signed Multiply Accumulate Dual Reverse. X specifies which halfword of the source register Rn is used as the multiply operand. If X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution” .
op{X}{cond} RdLo, RdHi, Rn, Rm where: op is one of: MLAL Signed Multiply Accumulate Long. SMLAL Signed Multiply Accumulate Long (halfwords, X and Y). X and Y specify which halfword of the source registers Rn and Rm are used as the first and second multiply operand: If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
These instructions do not affect the condition code flags.
12.6.6.6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLSD Signed Multiply Subtract Dual. SMLSDX Signed Multiply Subtract Dual Reversed. SMLSLD Signed Multiply Subtract Long Dual. SMLSLDX Signed Multiply Subtract Long Dual Reversed. SMLAW Signed Multiply Accumulate (word by halfword). If X is present, the multiplications are bottom × top and top × bottom.
SMLSDX R1, R3, R2, R0 ; ; ; ; SMLSLD R3, R6, R2, R7 ; ; ; ; SMLSLDX R3, R6, R2, R7 ; ; ; ; Multiplies bottom halfword of R3 with top halfword of R2, multiplies top halfword of R3 with bottom halfword of R2, subtracts second from first, adds R0, writes to R1 Multiplies bottom halfword of R6 with bottom halfword of R2, multiplies top halfword of R6 with top halfword of R2, subtracts second from first, adds R6:R3, writes to R6:R3 Multiplies bottom halfword of R6 with top halfword of R2, multiplies top halfwo
12.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: op is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. If the X is omitted, the multiplications are bottom × bottom and top × top. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated.
SMMLS 12.6.6.8 R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits, ; subtracts R8, truncates and writes to R4. SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where: op is one of: SMMUL Signed Most Significant Word Multiply. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted.
If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand.
Examples SMUAD R0, R4, R5 SMUADX R3, R7, R4 SMUSD R3, R6, R2 SMUSDX R4, R5, R3 ; ; ; ; ; ; ; ; ; ; ; ; Multiplies bottom halfword of R4 with the bottom halfword of R5, adds multiplication of top halfword of R4 with top halfword of R5, writes to R0 Multiplies bottom halfword of R7 with top halfword of R4, adds multiplication of top halfword of R7 with bottom halfword of R4, writes to R3 Multiplies bottom halfword of R4 with bottom halfword of R6, subtracts multiplication of top halfword of R6 with t
RdHi and RdLo must be different registers.
12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers.
12.6.6.12 SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm.
12.6.7 Saturating Instructions The table below shows the saturating instructions. Table 12-22.
12.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 31 for USAT.
12.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 15 for USAT.
QADD8 Saturating four 8-bit integer additions. QADD16 Saturating two 16-bit integer additions. QSUB Saturating 32-bit subtraction. QSUB8 Saturating four 8-bit integer subtraction. QSUB16 Saturating two 16-bit integer subtraction. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands.
Examples QADD16 12.6.7.
QASX QSAX 12.6.7.5 R7, R4, R2 ; ; ; ; ; R0, R3, R5 ; ; ; ; Adds top halfword of R4 to bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top highword of R2 from bottom halfword of R4, saturates to 16 bits and writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R3 to top halfword of R5, saturates to 16 bits, writes to bottom halfword of R0.
Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm, Rn are registers holding the first and second operands. Operation The QDADD instruction: Doubles the second operand value. Adds the result of the doubling to the signed saturated value in the first operand. Writes the result to the destination register.
12.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type is one of: UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UQASX instruction: 1.
Examples UQASX R7, R4, R2 UQSAX R0, R3, R5 12.6.7.7 ; ; ; ; ; ; ; ; Adds top halfword of R4 with bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4, saturates to 16 bits, writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R4 to top halfword of R5 saturates to 16 bits, writes to bottom halfword of R0.
These instructions do not affect the condition code flags.
12.6.8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data. Table 12-23.
12.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: op is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register Rm is the second operand register holding the value to be optionally shifted. imm is the shift length.
Examples PKHBT R3, R4, R5 LSL #0 PKHTB R4, R0, R2 ASR #1 12.6.8.2 ; ; ; ; ; ; Writes bottom halfword of R4 to bottom halfword of R3, writes top halfword of R5, unshifted, to top halfword of R3 Writes R2 shifted right by 1 bit to bottom halfword of R4, and writes top halfword of R0 to top halfword of R4. SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: op is one of: SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH R4, R6, ROR #16 UXTB R3, R10 12.6.8.3 ; ; ; ; Rotates R6 right by 16 bits, obtains bottom halfword of of result, sign extends to 32 bits and writes to R4 Extracts lowest byte of value in R10, zero extends, and writes to R3. SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: op is one of: SXTAB Sign extends an 8-bit value to a 32-bit value and add. SXTAH Sign extends a 16-bit value to a 32-bit value and add.
These instructions do not affect the flags. Examples SXTAH UXTAB R4, R8, R6, ROR #16 ; ; ; R3, R4, R10 ; ; Rotates R6 right by 16 bits, obtains bottom halfword, sign extends to 32 bits, adds R8,and writes to R4 Extracts bottom byte of R10 and zero extends to 32 bits, adds R4, and writes to R3.
12.6.9 Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields. Table 12-24.
12.6.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register.
12.6.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb.
12.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits.
12.6.10 Branch and Control Instructions The table below shows the branch and control instructions. Table 12-25.
12.6.10.1 B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional Execution” . label is a PC-relative expression. See “PC-relative Expressions” . Rm is a register that indicates an address to branch to.
These instructions do not change the flags. Examples B BLE B.W BEQ BEQ.
12.6.10.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
12.6.10.3 IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. Condition Flags This instruction does not change the flags.
Restrictions The restrictions are: Rn must not be SP Rm must not be SP and must not be PC When any of these instructions is used inside an IT block, it must be the last instruction of the IT block. Condition Flags These instructions do not change the flags. Examples ADR.
; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) DCI ((CaseB - BranchTable_H)/2) DCI ((CaseC - BranchTable_H)/2) ; CaseA offset calculation ; Case
12.6.11 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions. Table 12-27.
12.6.11.1 BKPT Breakpoint. Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0–255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
Examples CPSID CPSID CPSIE CPSIE i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) 12.6.11.3 DMB Data Memory Barrier. Syntax DMB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DMB acts as a data memory barrier.
12.6.11.4 DSB Data Synchronization Barrier. Syntax DSB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. Condition Flags This instruction does not change the flags. Examples DSB ; Data Synchronisation Barrier 12.6.11.
12.6.11.6 MRS Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag.
Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR. See “Application Program Status Register” . Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
12.6.11.9 SEV Send Event. Syntax SEV{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power Management” . Condition Flags This instruction does not change the flags. Examples SEV ; Send Event 12.6.11.10SVC Supervisor Call.
12.6.11.11 WFE Wait For Event. Syntax WFE{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation WFE is a hint instruction.
System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. See Section 12.9 ”System Control Block (SCB)” System Timer (SysTick) The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter. See Section 12.
12.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports: Up to 35 interrupts. A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Level detection of interrupt signals. Dynamic reprioritization of interrupts. Grouping of priority values into group priority and subpriority fields. Interrupt tail-chaining.
12.8.2.1 NVIC Programming Hints The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 12-29.
12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 12-31. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read/Write 0x00000000 0XE000E180 Interrupt Clear-enable Register 0 NVIC_ICER0 Read/Write 0x00000000 ... ... ... ... ...
12.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA 23 22 21 20 SETENA 15 14 13 12 SETENA 7 6 5 4 SETENA These registers enable interrupts and show which interrupts are enabled. • SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. Notes: 1.
12.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA These registers disable interrupts, and show which interrupts are enabled. • CLRENA: Interrupt Clear-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled.
12.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. • SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending. Read: 0: Interrupt is not pending.
12.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. • CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: Removes the pending state from an interrupt. Read: 0: Interrupt is not pending.
12.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE These registers indicate which interrupts are active. • ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
12.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..8] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI3 23 22 21 20 PRI2 15 14 13 12 PRI1 7 6 5 4 PRI0 The NVIC_IPR0–NVIC_IPR8 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34].
12.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INTID 7 6 5 4 3 2 1 0 INTID Write to this register to generate an interrupt from the software. • INTID: Interrupt ID Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of 0x03 specifies interrupt IRQ3.
12.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions.
12.9.1 System Control Block (SCB) User Interface Table 12-32.
12.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 DISOOFP 8 DISFPCA 4 3 – 23 22 21 20 – 15 14 13 – 7 6 5 – 2 1 0 DISFOLD DISDEFWBUF DISMCYCINT The SCB_ACTLR provides disable bits for the following processor functions: • IT folding • Write buffer use for accesses to the default memory map • Interruption of multi-cycle instructions.
Reset: 0x000000000 31 30 29 28 27 26 19 18 25 24 17 16 9 8 1 0 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 3 2 PartNo 7 6 5 PartNo 4 Revision The SCB_CPUID register contains the processor part number, version, and implementation information. • Implementer: Implementer Code 0x41: ARM. • Variant: Variant Number It is the r value in the rnpn product revision identifier: 0x0: Revision 0. • Constant: Reads as 0xF Reads as 0xF.
12.9.1.
Write: 0: No effect. 1: Removes the pending state from the PendSV exception. • PENDSTSET: SysTick Exception Set-pending Write: 0: No effect. 1: Changes SysTick exception state to pending. Read: 0: SysTick exception is not pending. 1: SysTick exception is pending. • PENDSTCLR: SysTick Exception Clear-pending Write: 0: No effect. 1: Removes the pending state from the SysTick exception. This bit is Write-only. On a register read, its value is Unknown.
Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 1 0 TBLOFF 23 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 TBLOFF 6 5 4 The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000. • TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map. Bit [29] determines whether the vector table is in the code or SRAM memory region: 0: Code. 1: SRAM.
12.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 VECTKEYSTAT/VECTKEY 26 25 24 23 22 21 20 19 VECTKEYSTAT/VECTKEY 18 17 16 15 ENDIANNESS 14 13 9 PRIGROUP 8 7 6 12 11 10 4 3 2 – 5 – 1 VECTCLRACTI SYSRESETREQ VE 0 VECTRESET The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system.
Interrupt Priority Level Value, PRI_N[7:0] PRIGROUP Binary Point 0b101 (1) Number of Group Priority Bits Subpriority Bits Group Priorities Subpriorities bxx.yyyyyy [7:6] [5:0] 4 64 0b110 bx.yyyyyyy [7] [6:0] 2 128 0b111 b.yyyyyyy None [7:0] 1 256 Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field.
12.9.1.6 System Control Register Name: SCB_SCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 SLEEPDEEP 1 SLEEPONEXIT 0 – – 23 22 21 20 – 15 14 13 12 – 7 6 – 5 4 SEVONPEND • SEVONPEND: Send Event on Pending Bit 0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
12.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 12 11 10 9 STKALIGN 8 BFHFNMIGN 4 3 2 DIV_0_TRP UNALIGN_TRP – – 23 22 21 20 – 15 14 13 – 7 6 5 – 1 0 USERSETMPE NONBASETHR ND DENA The SCB_CCR controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore BusFaults.
If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND: Unprivileged Software Access Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register” : 0: Disable. 1: Enable. • NONBASETHRDENA: Thread Mode Enable Indicates how the processor enters Thread mode: 0: The processor can enter the Thread mode only when no exception is active.
12.9.1.8 System Handler Priority Registers The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 12-33.
12.9.1.9 System Handler Priority Register 1 Name: SCB_SHPR1 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 PRI_6 15 14 13 12 PRI_5 7 6 5 4 PRI_4 • PRI_6: Priority Priority of system handler 6, UsageFault. • PRI_5: Priority Priority of system handler 5, BusFault. • PRI_4: Priority Priority of system handler 4, MemManage.
12.9.1.10 System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – • PRI_11: Priority Priority of system handler 11, SVCall.
12.9.1.11 System Handler Priority Register 3 Name: SCB_SHPR3 Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_15 23 22 21 20 PRI_14 15 14 13 12 – 7 6 5 4 – • PRI_15: Priority Priority of system handler 15, SysTick exception. • PRI_14: Priority Priority of system handler 14, PendSV.
12.9.1.
1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • SYSTICKACT: SysTick Exception Active Read: 0: The exception is not active. 1: The exception is active.
12.9.1.13 Configurable Fault Status Register Name: SCB_CFSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 DIVBYZERO 24 UNALIGNED 21 20 19 NOCP 18 INVPC 17 INVSTATE 16 UNDEFINSTR 13 12 STKERR 11 UNSTKERR 10 IMPRECISERR 9 PRECISERR 8 IBUSERR 5 MLSPERR 4 MSTKERR 3 MUNSTKERR 2 – 1 DACCVIOL 0 IACCVIOL – 23 22 – 15 BFARVALID 14 7 MMARVALID 6 – – • IACCVIOL: Instruction Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister” .
• MLSPERR: MemManage during Lazy State Preservation This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No MemManage fault occurred during the floating-point lazy state preservation. 1: A MemManage fault occurred during the floating-point lazy state preservation. • MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: The value in SCB_MMFAR is not a valid fault address.
• STKERR: Bus Fault on Stacking for Exception Entry This is part of “BFSR: Bus Fault Status Subregister” . 0: No stacking fault. 1: Stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR. • BFARVALID: Bus Fault Address Register (BFAR) Valid flag This is part of “BFSR: Bus Fault Status Subregister” .
This is part of “UFSR: Usage Fault Status Subregister” . 0: No unaligned access fault, or unaligned access trapping not enabled. 1: The processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
12.9.1.14 Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UFSR 23 22 21 20 UFSR 15 14 13 12 BFSR 7 6 5 4 MMFSR • MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 12.9.1.13.
12.9.1.15 Hard Fault Status Register Name: SCB_HFSR Access: Read/Write Reset: 0x000000000 31 DEBUGEVT 30 FORCED 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 VECTTBL 0 – – 20 – 15 14 13 12 – 7 6 5 4 – The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but wrting a 1 to any bit clears that bit to 0.
12.9.1.16 MemManage Fault Address Register Name: SCB_MMFAR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_MMFAR contains the address of the location that generated a memory management fault.
12.9.1.17 Bus Fault Address Register Name: SCB_BFAR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_BFAR contains the address of the location that generated a bus fault. • ADDRESS: Bus Fault Generation Location Address When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault.
12.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops.
12.10.1 System Timer (SysTick) User Interface Table 12-34.
12.10.1.1 SysTick Control and Status Name: SYST_CSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 – 23 22 21 20 – 19 18 17 16 COUNTFLAG 15 14 13 12 11 10 9 8 3 2 CLKSOURCE 1 TICKINT 0 ENABLE – 7 6 5 4 The SysTick SYST_CSR enables the SysTick features. • COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. • CLKSOURCE: Clock Source Indicates the clock source: 0: External Clock. 1: Processor Clock.
12.10.1.2 SysTick Reload Value Registers Name: SYST_RVR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 RELOAD The SYST_RVR specifies the start value to load into the SYST_CVR. • RELOAD: SYST_CVR Load Value Value to load into the SYST_CVR when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF.
12.10.1.3 SysTick Current Value Register Name: SYST_CVR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT The SysTick SYST_CVR contains the current value of the SysTick counter. • CURRENT: SysTick Counter Current Value Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
12.10.1.4 SysTick Calibration Value Register Name: SYST_CALIB Access: Read/Write Reset: 0x000030D4 31 NOREF 30 SKEW 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS The SysTick SYST_CSR indicates the SysTick calibration properties. • NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided. 1: No reference clock provided.
12.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: Independent attribute settings for each region Overlapping regions Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines: Eight separate memory regions, 0–7 A background region.
The table below shows the encodings for the TEX, C, B, and S access permission bits. Table 12-36. TEX C 0 TEX, C, B, and S Encoding B 0 1 S Memory Type Shareability Other Attributes x (1) Strongly-ordered Shareable – x (1) Device Shareable – Normal Not shareable 0 0 b000 1 Outer and inner write-through. No write allocate.
Table 12-38 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 12-38.
The software must use memory barrier instructions: Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings After the MPU setup, if it includes memory transfers that must use the new MPU settings.
12.11.1.5 Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead.
for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations of the memory device manufacturer.
12.11.2 Memory Protection Unit (MPU) User Interface Table 12-40.
12.11.2.1 MPU Type Register Name: MPU_TYPE Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEPARATE – 23 22 21 20 IREGION 15 14 13 12 DREGION 7 6 5 4 – The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. • IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00.
12.11.2.2 MPU Control Register Name: MPU_CTRL Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 PRIVDEFENA 1 HFNMIENA 0 ENABLE – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
When ENABLE and PRIVDEFENA are both set to 1: • For privileged accesses, the default memory map is as described in “Memory Model” . Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
12.11.2.3 MPU Region Number Register Name: MPU_RNR Access: Read/Write Reset: 0x00000800 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs. • REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs.
12.11.2.4 MPU Region Base Address Register Name: MPU_RBAR Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.5 MPU Region Attribute and Size Register Name: MPU_RASR Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
• SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.6 MPU Region Base Address Register Alias 1 Name: MPU_RBAR_A1 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.7 MPU Region Attribute and Size Register Alias 1 Name: MPU_RASR_A1 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
• SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.8 MPU Region Base Address Register Alias 2 Name: MPU_RBAR_A2 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.9 MPU Region Attribute and Size Register Alias 2 Name: MPU_RASR_A2 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
• SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.11.2.10MPU Region Base Address Register Alias 3 Name: MPU_RBAR_A3 Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
12.11.2.11 MPU Region Attribute and Size Register Alias 3 Name: MPU_RASR_A3 Access: Read/Write Reset: 0x00000000 31 23 30 – 29 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 6 5 4 – The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions.
• SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
12.12 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort Aligned Banked register Base register A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned.
Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception.
Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” . Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory” .
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.
13. Debug and Test Features 13.1 Description The SAM4 series microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 13.
13.3 Application Examples 13.3.1 Debug Environment Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 13-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 13.3.
Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM4 Chip 2 Chip 1 SAM4-based Application Board In Test 13.4 Debug and Test Pin Description Table 13-1.
13.5 Functional Description 13.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kW,so that it can be left unconnected for normal operation.
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 13-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI - TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low.
CPI (all instruction cycles except for the first cycle) Interrupt overhead 13.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels: Software trace: Software can write directly to ITM stimulus registers.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 13.5.7 IEEE® 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up, and must be kept in this state during the whole boundary scan operation.
13.5.8 ID Code Register Access: Read-only 31 30 29 28 27 21 20 19 PART NUMBER VERSION 23 22 15 14 13 PART NUMBER 7 6 5 12 11 4 3 MANUFACTURER IDENTITY 26 25 PART NUMBER 24 18 16 17 10 9 MANUFACTURER IDENTITY 2 1 8 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM4S 0x05B32 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.
14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: processor reset line. It also resets the Watchdog Timer. periph_nreset: affects the whole set of embedded peripherals nrst_out: drives the NRST pin These reset signals are asserted by the Reset Controller, either on external events or on software action.
named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.
14.4.4.2 Backup Reset A Backup Reset occurs when the chip exits from Backup Mode. While exiting Backup Mode, the vddcore_nreset signal is asserted by the Supply Controller. Field RSTTYP in the RSTC_SR is updated to report a Backup Reset. 14.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.
When the WDRSTEN in the WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-6. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.4.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR.
14.5 Reset Controller (RSTC) User Interface Table 14-1.
14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1400 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect.
14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1404 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1408 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset.
15. Real-time Timer (RTT) 15.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler driven from the 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the RTC 1 Hz signal, thus taking advantage of a calibrated 1 Hz clock.
15.4 Functional Description The programmable 16-bit prescaler value can be configured in the field RTPRES of the Real-time Timer Mode Register (RTT_MR). Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1 Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0.
Figure 15-2. RTT Counting APB cycle APB cycle SLCK RTPRES - 1 Prescaler 0 RTT 0 ...
15.5 Real-time Timer (RTT) User Interface Table 15-1.
15.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RTC1HZ 23 – 22 – 21 – 20 RTTDIS 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SLCK period.
15.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1434 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. Note: The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value.
15.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1438 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
15.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E143C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
16. Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
16.3 Block Diagram Figure 16-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Time Wave Generator Date RTCOUT0 RTCOUT1 Clock Calibration APB 16.4 User Interface Entry Control Alarm Interrupt Control RTC Interrupt Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller.
16.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. If only the “seconds” field is enabled, then an alarm is generated every minute.
The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted by TDERRCLR bit in RTC_SCCR. 16.5.6 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register (RTC_CR).
Figure 16-2.
16.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C).
32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking character like “:” for basic time display (hour, minute) on TN LCDs. Selection choice 5 provides a toggling signal when the RTC alarm is reached. Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs and immediately cleared when software clears the alarm interrupt source.
16.6 Real-time Clock (RTC) User Interface Table 16-1.
16.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1460 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • UPDTIM: Update Request Time Register 0: No effect.
16.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1464 Access: Read/Write 31 30 – – 23 22 – 29 28 27 TPERIOD 21 20 19 OUT1 15 14 13 26 – 18 – 12 HIGHPPM 11 25 24 THIGH 17 16 OUT0 10 9 8 CORRECTION 7 6 5 4 3 2 1 0 – – – NEGPPM – – PERSIAN HRMOD This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected.
The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
• THIGH: High Duration of the Output Pulse Value Name Description 0 H_31MS 31.2 ms 1 H_16MS 15.6 ms 2 H_4MS 3.91 ms 3 H_976US 976 µs 4 H_488US 488 µs 5 H_122US 122 µs 6 H_30US 30.5 µs 7 H_15US 15.
16.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1468 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units.
16.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E146C Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19–20 (gregorian) or 13–14 (persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00–99 (BCD).
16.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1470 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 11 MIN 7 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
16.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1474 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
16.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1478 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN): Time and calendar registers cannot be updated. 1 (UPDATE): Time and calendar registers can be updated.
16.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E147C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect.
16.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1480 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect.
16.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1484 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect.
16.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1488 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
16.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E148C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.
17.3 Block Diagram Figure 17-1.
17.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 17-2.
17.5 Watchdog Timer (WDT) User Interface Table 17-1.
17.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0x400E1450 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog if KEY is written to 0xA5. • KEY: Password. Value 0xA5 Name Description PASSWD Writing any other value in this field aborts the write operation.
17.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0x400E1454 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV Note: The first write access prevents any further modification of the value of this register, read accesses remain possible.
• WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
17.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0x400E1458 Access Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
18. Supply Controller (SUPC) The Supply Controller (SUPC) controls the supply voltages of the system and manages the backup low-power mode. In this mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is possible on multiple wake-up sources. The SUPC also generates the slow clock by selecting either the low-power RC oscillator or the low-power crystal oscillator. 18.
18.2 Block Diagram Figure 18-1.
18.3 Supply Controller Functional Description 18.3.1 Supply Controller Overview The device is divided into two power supply areas: The backup VDDIO power supply that includes the Supply Controller, a part of the Reset Controller, the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the Real-time Clock.
18.3.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
A supply monitor detection either generates a reset of the core power supply or a wake-up of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in SUPC_SMMR. Waking up the core power supply when a supply monitor detection occurs can be enabled by writing the SMEN bit to 1 in the Supply Controller Wake-up Mode register (SUPC_WUMR).
Figure 18-3. Raising the VDDIO Power Supply TON Voltage 7 x Slow Clock Cycles (5 for startup slow RC + 2 for synchro.) Regulator 3 x Slow Clock 2 x Slow Clock Cycles Cycles 6.5 x Slow Clock Cycles Zero-Power POR Backup Power Supply Zero-Power Power-On Reset Cell output 22 - 42 kHz RC Oscillator output vr_on Core Power Supply Fast RC Oscillator output bodcore_in vddcore_nreset RSTC.ERSTL default = 2 NRST (no ext.
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The BODRSTS bit is set in SUPC_SR so that the user can know the source of the last reset. Until bodcore_in is deactivated, the vddcore_nreset signal remains active. 18.3.7 Wake-up Sources The wake-up events allow the device to exit backup mode.
allows the user to identify the source of the wake-up, however, if a new wake-up condition occurs, the primary information is lost. No new wake-up can be detected since the primary wake-up condition has disappeared. 18.3.7.2 Low-power Tamper Detection and Anti-Tampering Low-power debouncer inputs (WKUP0, WKUP1) can be used for tamper detection.
Figure 18-6. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors) MCU RTCOUTx WKUP0 WKUP1 Pull-down Resistors GND GND GND The debouncing period duration is configurable. The period is made for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer). The number of successive identical samples to wake up the system can be configured from 2 up to 8 in the LPDBC field of SUPC_WUMR.
Figure 18-7. Using WKUP Pins Without RTCOUTx Pins VDDIO MCU Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND 18.3.7.3 Clock Alarms The RTC and the RTT alarms can generate a wake-up of the core power supply. This can be enabled by writing, respectively, the bits RTCEN and RTTEN to 1 in SUPC_WUMR. The Supply Controller does not provide any status as the information is available in the user interface of either the RealTime Timer or the Real-Time Clock. 18.3.7.
18.3.
18.4 Supply Controller (SUPC) User Interface The user interface of the Supply Controller is part of the System Controller user interface. 18.4.1 System Controller (SYSC) User Interface Table 18-1.
18.4.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1410 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). VROFF: Voltage Regulator Off 0 (NO_EFFECT): No effect.
18.4.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1414 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
18.4.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1418 Access: Read/Write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 14 ONREG 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
18.4.6 Supply Controller Wake-up Mode Register Name: SUPC_WUMR Address: 0x400E141C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LPDBC 16 15 – 14 13 WKUPDBC 12 11 – 10 – 9 – 8 – 7 LPDBCCLR 6 LPDBCEN1 5 LPDBCEN0 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 – This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).
WKUPDBC: Wake-up Inputs Debouncer Period Value Name Description 0 IMMEDIATE 1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods Immediate, no debouncing, de
18.4.
18.4.
0 (RC): The slow clock, SLCK is generated by the embedded 32 kHz RC oscillator. 1 (CRYST): The slow clock, SLCK is generated by the 32 kHz crystal oscillator. LPDBCS0: Low-power Debouncer Wake-up Status on WKUP0 0 (NO): No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
18.4.9 System Controller Write Protection Mode Register Name: SYSC_WPMR Access: Read/Write Reset: See Table 18-1 ”System Controller Registers” 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
19. General-Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds 8 General-purpose Backup registers. It is possible to generate an immediate clear of the content of General-purpose Backup registers 0 to 3 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other General-purpose Backup registers (second half) remains unchanged. The Supply Controller module must be programmed accordingly.
19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Offset 0x0 ... 0x1C Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 7 SYS_GPBR7 Access Reset Read-write – ... ...
19.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1490 Access: Read-write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE • GPBR_VALUE: Value of GPBR x If a Tamper event has been detected, it is not possible to write GPBR_VALUE as long as the LPDBCS0 or LPDBCS1 flags have not been cleared in Supply Controller Status register SUPC_SR.
20. Enhanced Embedded Flash Controller (EEFC) 20.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
20.4 Functional Description 20.4.1 Embedded Flash Organization The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of: One memory plane organized in several pages of the same size. Two 128-bit or 64-bit read buffers used for code read optimization. One 128-bit or 64-bit read buffer used for data read optimization. One write buffer that manages page programming. The write buffer size is equal to the page size.
20.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
Figure 20-3. Code Read Optimization for FWS = 3 Master Clock ARM Request (32-bit) @Byte 0 @4 Flash Access Bytes 0-15 @20 @24 Bytes 16-31 @28 @32 @36 @40 Bytes 32-47 XXX @48 @52 Bytes 32-47 XXX Data To ARM @44 Bytes 48-63 Bytes 0-15 Buffer 1 (128bits) 20.4.2.
20.4.2.4 Data Read Optimization The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 20-5). The data read optimization is enabled by default.
20.4.3 Flash Commands The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock regions, consecutive programming, locking and full Flash erasing, etc. Table 20-2.
Figure 20-6.
20.4.3.1 Get Flash Descriptor Command This command provides the system with information on the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR.
When Flash programming is completed, the FRDY bit in EEFC_FSR rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the EEFC is activated. Three errors can be detected in EEFC_FSR after a programming sequence: Command Error: a bad keyword has been written in EEFC_FCR. Lock Error: the page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.
Figure 20-7.
Figure 20-8.
Figure 20-9.
When programming is completed, the FRDY bit in EEFC_FSR rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after a programming sequence: 20.4.3.4 Command Error: a bad keyword has been written in EEFC_FCR. Lock Error: at least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased.
When the GPNVM bit is set, the bit FRDY in EEFC_FSR rises. If an interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated. The result of the SGPB command can be checked by running a Get GPNVM bit (GGPB) command. Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit.
The RC calibration for the 4 MHz is set to ‘1000000’. 20.4.3.7 Security Bit Protection When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast Flash Programming interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed.
When programming is completed, the FRDY bit in EEFC_FSR rises. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence: Command Error: a bad keyword has been written in EEFC_FCR. Flash Error: at the end of the programming, the EraseVerify test of the Flash memory has failed.
20.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00. Table 20-6.
20.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 (0), 0x400E0C00 (1) Access: Read/Write Offset: 0x00 31 30 29 28 27 26 25 24 – – – – – CLOE – FAM 23 22 21 20 19 18 17 16 – – – – – – – SCOD 15 14 13 12 11 10 9 8 – – – – 7 6 5 4 3 2 1 0 – – – – – – – FRDY FWS • FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt.
20.5.
• FARG: Flash Command Argument GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased.
20.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 (0), 0x400E0C08 (1) Access: Read-only Offset: 0x08 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – FLERR FLOCKE FCMDE FRDY • FRDY: Flash Ready Status 0: The EEFC is busy. 1: The EEFC is ready to start a new command.
20.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C (0), 0x400E0C0C (1) Access: Read-only Offset: 0x0C 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
21. Fast Flash Programming Interface (FFPI) 21.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
21.3 Parallel Fast Flash Programming 21.3.1 Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left unconnected. Figure 21-1. SAM4SxB/C Parallel Programming Interface VDDIO VDDIO VDDIO TST PGMEN0 PGMEN1 VDDCORE NCMD RDY PGMNCMD PGMRDY NOE PGMNOE NVALID Table 21-1.
Table 21-1.
Table 21-3. Command Bit Coding (Continued) DATA[15:0] Symbol Command Executed 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version 21.3.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: Apply the supplies as described in Table 21-1. Apply XIN clock within TPOR_RESET if an external clock is available.
Figure 21-3. Parallel Programming Timming, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 21-4.
Figure 21-5. Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 NVALID 11 7 6 4 Adress IN DATA[15:0] Z 8 Data OUT 10 X IN 1 MODE[3:0] Table 21-5.
21.3.5.1 Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 21-6. 21.3.5.
writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 21.3.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes.
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when bit n of the bit mask is set.. Table 21-12. Get GP NVM Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE GGPB GP NVM Bit Mask Status 2 Read handshaking DATA 0 = GP NVM bit is cleared 1 = GP NVM bit is set 21.3.5.6 Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE).
Table 21-14. 21.3.5.8 Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[15:0] n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ ... ... ... ... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-15.
22. Cortex-M Cache Controller (CMCC) 22.1 Description The Cortex-M Cache Controller (CMCC) is a four-way set associative unified cache controller. It integrates a controller, a tag directory, data memory, metadata memory and a configuration interface. 22.
22.3 Block Diagram Figure 22-1. Block Diagram Cortex M Memory Interface Bus Cortex M Interface Cache Controller APB Interface METADATA RAM RAM Interface Registers Interface DATA RAM TAG RAM Memory Interface System Memory Bus 22.4 Functional Description 22.4.1 Cache Operation On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated with its configuration registers.
22.4.2.2 3. Perform an invalidate by line writing the bit set {index, way} in the CMCC_MAINT1 register. 4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register. Cache Invalidate All Operation To invalidate all cache entries: Write 1 to the INVALL field of the CMCC_MAINT0 register. 22.4.3 Cache Performance Monitoring The Cortex-M cache controller includes a programmable 32-bit monitor counter.
22.5 Cortex M Cache Controller (CMCC) User Interface Table 22-1.
22.5.1 Cache Controller Type Register Name: CMCC_TYPE Address: 0x4007C000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 CLSIZE 11 10 9 CSIZE 8 7 LCKDOWN 6 5 4 RRP 3 LRUP 2 RANDP 1 GCLK 0 AP WAYNUM • AP: Access Port Access Allowed 0: Access Port Access is disabled. 1: Access Port Access is enabled. • GCLK: Dynamic Clock Gating Supported 0: Cache controller does not support clock gating.
• LCKDOWN: Lock Down Supported 0: Lock Down is not supported. 1: Lock Down is supported.
22.5.2 Cache Controller Configuration Register Name: CMCC_CFG Address: 0x4007C004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 GCLKDIS • GCLKDIS: Disable Clock Gating 0: Clock gating is activated. 1: Clock gating is disabled.
22.5.3 Cache Controller Control Register Name: CMCC_CTRL Address: 0x4007C008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CEN • CEN: Cache Controller Enable 0: When set to 0, this field disables the cache controller. 1: When set to 1, this field enables the cache controller.
22.5.4 Cache Controller Status Register Name: CMCC_SR Address: 0x4007C00C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CSTS • CSTS: Cache Controller Status 0: When read as 0, this field indicates that the cache controller is disabled. 1: When read as 1, this field indicates that the cache controller is enabled.
22.5.5 Cache Controller Maintenance Register 0 Name: CMCC_MAINT0 Address: 0x4007C020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INVALL • INVALL: Cache Controller Invalidate All 0: No effect. 1: When set to 1, this field invalidates all cache entries.
22.5.6 Cache Controller Maintenance Register 1 Name: CMCC_MAINT1 Address: 0x4007C024 Access: Write-only 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INDEX 7 6 5 4 3 – 2 – 1 – 0 – WAY INDEX • INDEX: Invalidate Index This field indicates the cache line that is being invalidated.
22.5.
22.5.8 Cache Controller Monitor Enable Register Name: CMCC_MEN Address: 0x4007C02C Access: Write-only Reset: 0x00002000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MENABLE • MENABLE: Cache Controller Monitor Enable 0: When set to 0, the monitor counter is disabled. 1: When set to 1, the monitor counter is activated.
22.5.9 Cache Controller Monitor Control Register Name: CMCC_MCTRL Address: 0x4007C030 Access: Write-only Reset: 0x00002000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Monitor 0: No effect. 1: When set to 1, this field resets the event counter register.
22.5.
23. Cyclic Redundancy Check Calculation Unit (CRCCU) 23.1 Description The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus Matrix. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16. The CRCCU is designed to perform data integrity checks of off-/on-chip memories as a background task wthout CPU intervention. 23.
23.3 CRCCU Block Diagram Figure 23-1.
23.4 Product Dependencies 23.4.1 Power Management The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the CRCCU in the PMC to enable the CRCCU clock. 23.4.2 Interrupt Source The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires programming the Interrupt Controller before configuring the CRCCU.
23.5 CRCCU Functional Description 23.5.1 CRC Calculation Unit The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this CRC engine performs a checksum computation on a memory area. CRC computation is performed from the LSB to MSB. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16 (see field description ”PTYPE: Primitive Polynomial” in Section 23.7.10 ”CRCCU Mode Register” for details). 23.5.
23.6 Transfer Control Registers Memory Mapping Table 23-2. Transfer Control Register Memory Mapping Offset Register Name Access CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read/Write CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read/Write CRCCU_DSCR + 0xC - 0x10 Reserved – – CRCCU_DSCR+0x10 CRCCU Transfer Reference Register TR_CRC Read/Write Note: These registers are memory mapped.
23.6.
23.6.
23.6.3 Transfer Reference Register Name: TR_CRC Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 REFCRC 23 22 21 20 REFCRC 15 14 13 12 REFCRC 7 6 5 4 REFCRC • REFCRC: Reference CRC When Compare mode is enabled, the checksum is compared with this field.
23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface Table 23-3.
23.7.1 CRCCU Descriptor Base Address Register Name: CRCCU_DSCR Access: Read/Write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 3 – 2 – 1 – 8 – 0 – DSCR 23 22 21 20 DSCR 15 14 13 7 – 6 – 5 – 12 DSCR 4 – • DSCR: Descriptor Base Address DSCR needs to be aligned with 512-byte boundaries.
23.7.
23.7.
23.7.
23.7.
23.7.
23.7.
23.7.8 CRCCU DMA Interrupt Status Register Name: CRCCU_DMA_ISR Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAISR • DMAISR: Interrupt Status register 0: DMA buffer transfer has not yet started or transfer still in progress 1: DMA buffer transfer has terminated. This flag is reset after read.
23.7.
23.7.10 CRCCU Mode Register Name: CRCCU_MR Access: Read Write Reset: 31 – 23 – 15 – 7 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIVIDER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 PTYPE 25 – 17 – 9 – 1 COMPARE 24 – 16 – 8 – 0 ENABLE • ENABLE: CRC Enable • COMPARE: CRC Compare If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value stored in the TR_CRC reference register.
23.7.11 CRCCU Status Register Name: CRCCU_SR Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC 23 22 21 20 CRC 15 14 13 12 CRC 7 6 5 4 CRC • CRC: Cyclic Redundancy Check Value This register can not be read if the COMPARE field of the CRC_MR is set to true.
23.7.
23.7.
23.7.
23.7.
24. SAM4S Boot Program 24.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 24.2 Hardware and Software Constraints SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code. USB Requirements: 11,289 MHz 12,000 MHz 16,000 MHz 18,432 MHz UART0 requirements: None Note: 1. Table 24-1. 24.
24.4 Device Initialization Initialization follows the steps described below: 1. Stack setup 2. Setup the Embedded Flash Controller 3. External Clock detection (crystal or external clock on XIN) 4. If external crystal or clock with supported frequency, allow USB activation 5. Else, does not allow USB activation and use internal 12 MHz RC oscillator 6. Main oscillator frequency detection if no external clock detected 7. Switch Master Clock on Main Oscillator 8. C variable initialization 9.
24.5 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 24-2. Table 24-2.
Get Version (V): Return the SAM-BA boot version Output: ‘>’ 24.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product.
The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For More details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum: http://www.usb.org/developers/vendor/VID_Only_Form_withCCAuth_102407b.
24.5.4 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash.
25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing overall bandwidth. The Bus Matrix interconnects AHB masters to AHB slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the accessed slave which is connected directly (zero cycle latency).
Table 25-3. 25.3 Master to Slave Access 2 Internal Flash X – - X 3 External Bus Interface – X X X 4 Peripheral Bridge – X X – Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Thus it is possible to boot at the same address while using different AHB slaves. 25.
Each algorithm may be complemented by selecting a default master configuration for each slave. In case of re-arbitration, specific conditions apply. See Section 25.5.1 “Arbitration Rules“. 25.5.1 Arbitration Rules Each arbiter has the ability to arbitrate between requests of two or more masters. To avoid burst breaking and to provide the maximum throughput for slave interfaces, arbitration should take place during the following cycles: 25.5.1.1 1.
25.5.2.2 Round-Robin arbitration with last access master Round-robin arbitration with last access master is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other non-privileged masters incur one latency cycle if they want to access the same slave.
25.8 Bus Matrix (MATRIX) (MATRIX) User Interface Table 25-4.
25.8.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0..
25.8.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0..MATRIX_SCFG4 Address: 0x400E0240 Access: Read/Write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 FIXED_DEFMSTR 25 24 ARBT 17 16 DEFMSTR_TYPE SLOT_CYCLE • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reach for a burst, it may be broken by another master trying to access this slave.
25.8.3 Bus Matrix Priority Registers For Slaves Name: MATRIX_PRAS0..
15 14 – – 7 6 – – 13 12 M3PR 5 4 M1PR 11 10 – – 3 2 – – 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of master x for accessing the selected slave. The higher the number, the higher the priority. 25.8.
Address: 0x400E0314 Access Read/Write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SYSIO12 SYSIO11 SYSIO10 – – 7 6 5 4 3 2 1 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – – • SYSIO4: PB4 or TDI Assignment 0: TDI function selected. 1: PB4 function selected. • SYSIO5: PB5 or TDO/TRACESWO Assignment 0: TDO/TRACESWO function selected. 1: PB5 function selected.
Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0 • SMC_NFCS0: SMC NAND Flash Chip Select 0 Assignment 0: NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0) 1: NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0) • SMC_NFCS1: SMC NAND Flash Chip Select 1 Assig
25.8.6 Write Protection Mode Register Name: MATRIX_WPMR Address: 0x400E03E4 Access: Read/Write Reset: See Table 25-4 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). See Section 25.
25.8.7 Write Protection Status Register Name: MATRIX_WPSR Address: 0x400E03E8 Access: Read-only Reset: See Table 25-4 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the MATRIX_WPSR.
26. Static Memory Controller (SMC) 26.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M4 based device. The External Bus Interface of the SAM4S consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
26.3 I/O Lines Description Table 26-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Signal Output Low A[23:0] Address Bus Output D[7:0] Data Bus NWAIT External Wait Signal NANDCS I/O Input Low NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low 26.4 Product Dependencies 26.4.
Figure 26-1. Memory Connections for Four External Devices NCS[0] - NCS[3] NRD SMC NWE A[23:0] D[7:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 24 8 26.6 A[23:0] D[7:0] Connection to External Devices 26.6.1 Data Bus Width The data bus width is 8 bits. Figure 26-2 shows how to connect a 512K x 8-bit memory on NCS0. Figure 26-2.
Figure 26-3. NAND Flash Signal Multiplexing on SMC Pins SMC NAND Flash Logic NCSx (activated if SMC_NFCSx=1) * NRD NANDOE NANDWE NANDOE NANDWE NWE * in CCFG_SMCNFCS Matrix register Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes.
Figure 26-4. Standard and “CE don’t care” NAND Flash Application Examples D[7:0] D[7:0] AD[7:0] A[22:21] A[22:21] ALE CLE NCSx NCSx CE SMC NAND Flash “CE don’t care” NAND Flash NANDOE NANDOE NOE NANDWE 26.7 ALE CLE Not Connected SMC AD[7:0] NOE NANDWE NWE PIO CE PIO R/B PIO NWE R/B Application Example 26.7.1 Implementation Examples Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability.
26.7.1.1 8-bit NAND Flash Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K K9F2G08U0M I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
26.7.1.2 NOR Flash Hardware Configuration D[0..7] A[0..
Figure 26-5. Standard Read Cycle MCK A[23:0] NRD NCS D[7:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NRD_HOLD NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE 26.8.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 26.8.1.2 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3.
Figure 26-6. No Setup, No Hold on NRD and NCS Read Signals MCK A[23:0] NRD NCS D[7:0] NRD_PULSE 26.8.1.5 NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE NRD_CYCLE Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 26.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus.
Figure 26-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[23:0] NRD NCS tPACC D[7:0] Data Sampling 26.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 26-8 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
26.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 26-9. The write cycle starts with the address setting on the memory address bus. 26.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 26.8.3.2 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3.
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 26.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 26-10). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 26-10.
Figure 26-11. WRITE_MODE = 1. The write operation is controlled by NWE MCK A[23:0] NWE NCS D[7:0] 26.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 26-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 26-12. WRITE_MODE = 0.
Section 26.15.4 ”SMC MODE Register” 26.8.6 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type.
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 446. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus.
Figure 26-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[23:0] NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[7:0] Read to Write Wait State Chip Select Wait State 26.10.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state.
Figure 26-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[23:0] NWE NRD no hold no setup D[7:0] write cycle Early Read wait state read cycle Figure 26-15.
Figure 26-16. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[7:0] write cycle Early Read read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 26.10.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
26.10.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 26-13 on page 446. 26.11 Data Float Wait States Some memory devices are slow to release the external bus.
Figure 26-17. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[23:0] NRD NCS tpacc D[7:0] TDF = 2 clock cycles NRD controlled read operation Figure 26-18. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[23:0] NRD NCS tpacc D[7:0] TDF = 3 clock cycles NCS controlled read operation 26.11.
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 26-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[7:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 26.11.
Figure 26-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[23:0] read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[7:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 26-21.
Figure 26-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[23:0] read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[7:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 26.12 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
26.12.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 26-23.
Figure 26-24.
26.12.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 26-25 and Figure 26-26. After deassertion, the access is completed: the hold step of the access is performed.
Figure 26-26.
26.12.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
26.13 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
26.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 26-29 on page 460. The external device may not be fast enough to support such timings. Figure 26-30 illustrates the recommended procedure to properly switch from one mode to the other. Figure 26-29.
26.14 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
In page mode, the programming of the read timings is described in Table 26-6: Table 26-6. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
Figure 26-32.
26.15 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 26-7. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 26-7, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 26-7.
26.15.1 SMC Setup Register Name: SMC_SETUP[0..
26.15.2 SMC Pulse Register Name: SMC_PULSE[0..
26.15.3 SMC Cycle Register Name: SMC_CYCLE[0..3] Address: 0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3] Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE • NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle.
26.15.4 SMC MODE Register Name: SMC_MODE[0..3] Address: 0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3] Access: Read-write 31 30 – – 29 28 23 22 21 20 – – – TDF_MODE 15 14 13 12 11 – – – – – 7 6 5 – – PS 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 10 9 8 – – – TDF_CYCLES 3 2 1 0 – – WRITE_MODE READ_MODE • READ_MODE: 1: The read operation is controlled by the NRD signal.
• TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. • TDF_MODE: TDF Optimization 1: TDF optimization is enabled.
26.15.5 SMC OCMS Mode Register Name: SMC_OCMS Address: 0x400E0080 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CS3SE 18 CS2SE 17 CS1SE 16 CS0SE 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 - 0 SMSE • CSxSE: Chip Select (x = 0 to 3) Scrambling Enable 0: Disable Scrambling for CSx. 1: Enable Scrambling for CSx.
26.15.6 SMC OCMS Key1 Register Name: SMC_KEY1 Address: 0x400E0084 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 • KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values.
26.15.7 SMC OCMS Key2 Register Name: SMC_KEY2 Address: 0x400E0088 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 • KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.
26.15.8 SMC Write Protect Mode Register Name: SMC_WPMR Address: 0x400E00E4 Access: Read-write Reset: See Table 26-7 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
26.15.9 SMC Write Protect Status Register Name: SMC_WPSR Address: 0x400E00E8 Type: Read-only Value: See Table 26-7 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register.
27. Peripheral DMA Controller (PDC) 27.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
27.3 Block Diagram Figure 27-1.
27.4 Functional Description 27.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full- or half-duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
These status flags are described in the Peripheral Status register (PERIPH_PTSR). 27.4.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix.
27.5 Peripheral DMA Controller (PDC) User Interface Table 27-1.
27.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the receiver.
27.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
27.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0: Stops peripheral data transfer to the transmitter.
27.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains the next receive buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains the next receive buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains the next transmit buffer address. When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
27.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains the next transmit buffer size. When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
27.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
27.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC receiver channel requests are disabled. 1: PDC receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC transmitter channel requests are disabled.
28. Clock Generator 28.1 Description The Clock Generator user interface is embedded within the Power Management Controller and is described in Section 29.17 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 28.
28.3 Block Diagram Figure 28-1.
It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR). 28.4.2 Slow Clock Crystal Oscillator The Clock Generator integrates a 32768 Hz low-power oscillator. To use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal. Two external capacitors must be wired as shown in Figure 28-2. More details are given in the section “DC Characteristics” of the product datasheet.
28.5 Main Clock Figure 28-3 shows the main clock block diagram. Figure 28-3. Main Clock Block Diagram CKGR_MOR MOSCRCEN CKGR_MOR MOSCRCF PMC_SR MOSCRCS Fast RC Oscillator CKGR_MOR PMC_SR MOSCSEL MOSCSELS 0 CKGR_MOR MAINCK Main Clock MOSCXTEN 1 3-20 MHz Crystal or Ceramic Resonator Oscillator XIN XOUT CKGR_MOR MOSCXTST PMC_SR 3-20 MHz Oscillator Counter SLCK Slow Clock MOSCXTS CKGR_MOR MOSCRCEN CKGR_MOR CKGR_MCFR MOSCXTEN RCMEAS CKGR_MOR MOSCSEL CKGR_MCFR MAINCK Main Clock Ref.
The software can disable or enable the 4/8/12 MHz fast RC oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). The user can also select the output frequency of the fast RC oscillator, either 4/8/12 MHz are available. It can be done through MOSCRCF bits in CKGR_MOR. When changing this frequency selection, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until the oscillator is stabilized.
28.5.4 Main Clock Oscillator Selection The user can select either the 4/8/12 MHz fast RC oscillator or the 3 to 20 MHz crystal or ceramic resonator-based oscillator to be the source of main clock. The advantage of the 4/8/12 MHz fast RC oscillator is that it provides fast start-up time, this is why it is selected by default (to start up the system) and when entering wait mode. The advantage of the 3 to 20 MHz crystal or ceramic resonator-based oscillator is that it is very accurate.
If MOSCSELS=0, the crystal oscillator can be disabled (MOSCXTEN=0 in the CKGR_MOR register). 28.5.7 Main Clock Frequency Counter The device features a main clock frequency counter that provides the frequency of the main clock.
28.6 Divider and PLL Block The device features two divider/two PLL Blocks that permit a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the frequency of the main clock. Figure 28-4 shows the block diagram of the dividers and PLL blocks. Figure 28-4.
Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master Clock Register (PMC_MCKR).
29. Power Management Controller (PMC) 29.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4 processor. The Supply Controller selects between the 32 kHz RC oscillator or the slow crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized.
29.3 Block Diagram Figure 29-1.
Figure 29-2. Master Clock Controller PMC_MCKR PMC_MCKR CSS PRES SLCK MAINCK Master Clock Prescaler PLLACK To the MCK Divider PLLBCK To the Processor Clock Controller (PCK) 29.5 Processor Clock Controller The PMC features a Processor Clock Controller (HCLK) that implements the processor sleep mode. The processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode Register (PMC_FSMR).
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1). When a peripheral clock is disabled, the clock is immediately stopped.
The fast start-up circuitry, as shown in Figure 29-4, is fully asynchronous and provides a fast start-up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the embedded 4/8/12 MHz fast RC oscillator restarts automatically. When entering wait mode, the embedded Flash can be placed in one of the low-power modes (deep-power-down or standby) depending on the configuration of the FLPM field in the PMC_FSMR.
The procedure and conditions to enter wait mode and the circuitry to exit wait mode are strictly the same as fast start-up (see Section 29.11 ”Fast Startup”). 29.13 Main Clock Failure Detector The clock failure detector monitors the main crystal oscillator or ceramic resonator-based oscillator to identify an eventual failure of this oscillator. The clock failure detector can be enabled or disabled by bit CFDEN in the PMC Clock Generator Main Oscillator Register (CKGR_MOR).
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Register (PMC_FOCR). 29.14 Programming Sequence 1. If the fast crystal oscillator is not required, PLL and Divider can be directly configured (Step 6.) else the fast crystal oscillator must be started (Step 2.). 2. Enable the fast crystal oscillator: The fast crystal oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR).
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This can be done either by polling MCKRDY in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in the PMC_IER. The PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows: If a new value for CSS field corresponds to PLL clock, Program the PRES field in PMC_MCKR.
9. Enable the peripheral clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR. 29.15 Clock Switching Details 29.15.1 Master Clock Switching Timings Table 29-1 and Table 29-2 give the worst case timings required for the master clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated.
29.15.2 Clock Switching Waveforms Figure 29-6. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 29-7.
Figure 29-8. Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 29-9.
29.16 Register Write Protection To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the “PMC Write Protection Mode Register” (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “PMC Write Protection Status Register” (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
29.17 Power Management Controller (PMC) User Interface Table 29-3.
Table 29-3. Register Mapping Offset Register Name 0x0110 Oscillator Calibration Register PMC_OCR 0114 - 0x120 Reserved 0134 - 0x144 Reserved Note: Access Reset Read/Write 0x0040_4040 – – – – – – If an offset is not listed in the table it must be considered as “reserved”.
29.17.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0400 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • UDP: USB Device Port Clock Enable 0: No effect. 1: Enables the 48 MHz clock (UDPCK) of the USB Device Port.
29.17.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0404 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • UDP: USB Device Port Clock Disable 0: No effect. 1: Disables the 48 MHz clock (UDPCK) of the USB Device Port.
29.17.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0408 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UDP: USB Device Port Clock Status 0: The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1: The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
29.17.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0x400E0410 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0x400E0414 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0x400E0418 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled.
29.17.7 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0420 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 WAITMODE 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT.
At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz. Note: Value Name Description 0x0 4_MHz The Fast RC Oscillator Frequency is at 4 MHz (default) 0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz 0x2 12_MHz The Fast RC Oscillator Frequency is at 12 MHz MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR register. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time.
29.17.8 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0424 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.
29.17.9 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0428 Access: Read/Write 31 – 30 – 29 ONE 28 – 23 22 21 20 27 – 26 25 MULA 24 19 18 17 16 10 9 8 2 1 0 MULA 15 – 14 – 13 7 6 5 12 11 PLLACOUNT 4 3 DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
29.17.10PMC Clock Generator PLLB Register Name: CKGR_PLLBR Address: 0x400E042C Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 MULB 24 19 18 17 16 10 9 8 2 1 0 MULB 15 – 14 – 13 7 6 5 12 11 PLLBCOUNT 4 3 DIVB Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC. This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.11PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PLLBDIV2 12 PLLADIV2 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 – 1 0 CSS This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
• PLLBDIV2: PLLB Divisor by 2 PLLBDIV2 PLLB Clock Division 0 PLLB clock frequency is divided by 1. 1 PLLB clock frequency is divided by 2.
29.17.12PMC USB Clock Register Name: PMC_USB Address: 0x400E0438 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 – 0 USBS USBDIV 2 – This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • USBS: USB Input Clock Selection 0: USB Clock Input is PLLA.
29.17.13PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0440 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 1 CSS 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.
29.17.
29.17.16PMC Status Register Name: PMC_SR Address: 0x400E0468 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 FOS 19 CFDS 18 CFDEV 17 MOSCRCS 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 – 5 – 4 – 3 MCKRDY 2 LOCKB 1 LOCKA 0 MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0: Main XTAL oscillator is not stabilized. 1: Main XTAL oscillator is stabilized.
• MOSCRCS: Main On-Chip RC Oscillator Status 0: Main on-chip RC oscillator is not stabilized. 1: Main on-chip RC oscillator is stabilized. • CFDEV: Clock Failure Detector Event 0: No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. 1: At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR.
29.17.
29.17.18PMC Fast Start-up Mode Register Name: PMC_FSMR Address: 0x400E0470 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 LPM 19 – 18 USBAL 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 FLPM This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.19PMC Fast Start-up Polarity Register Name: PMC_FSPR Address: 0x400E0474 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” .
29.17.20PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0478 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output.
29.17.21PMC Write Protection Mode Register Name: PMC_WPMR Address: 0x400E04E4 Access: Read/Write Reset: See Table 29-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). See Section 29.
29.17.22PMC Write Protection Status Register Name: PMC_WPSR Address: 0x400E04E8 Access: Read-only Reset: See Table 29-3 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PMC_WPSR. 1: A write protection violation has occurred since the last read of the PMC_WPSR.
29.17.23PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0x400E0500 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • PIDx: Peripheral Clock x Enable 0: No effect.
29.17.24PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0x400E0504 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • PIDx: Peripheral Clock x Disable 0: No effect.
29.17.25PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0x400E0508 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – PID34 PID33 PID32 • PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled.
29.17.26PMC Oscillator Calibration Register Name: PMC_OCR Address: 0x400E0510 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 SEL12 22 21 20 19 CAL12 18 17 16 15 SEL8 14 13 12 11 CAL8 10 9 8 7 SEL4 6 5 4 3 CAL4 2 1 0 This register can only be written if the WPEN bit is cleared in “PMC Write Protection Mode Register” . • CAL4: RC Oscillator Calibration bits for 4 MHz Calibration bits applied to the RC Oscillator when SEL4 is set.
30. Chip Identifier (CHIPID) 30.1 Description Chip Identifier (CHIPID) registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
30.3 Chip Identifier (CHIPID) User Interface Table 30-2.
30.3.1 Chip ID Register Name: CHIPID_CIDR Address: 0x400E0740 Access: Read-only 31 EXT 30 23 22 29 NVPTYP 28 21 20 27 26 19 18 ARCH 15 14 13 6 EPROC 24 17 16 9 8 1 0 SRAMSIZ 12 11 NVPSIZ2 7 25 ARCH 10 NVPSIZ 5 4 3 2 VERSION • VERSION: Version of the Device Current version of the device.
Value Name Description 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved • NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved • SRAMSIZ: Internal SRAM Size Value Name Descripti
Value Name Description 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes • ARCH: Architecture Identifier Value Name Description 0x88 SAM4SxA SAM4SxA (48-pin version) 0x89 SAM4SxB SAM4SxB (64-pin version) 0x8A SAM4SxC SAM4SxC (100-pin version) • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory ROM and Embedded Flash Memory 3 ROM_FLASH NVPSIZ is ROM
30.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0744 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the EXT bit in CHIPID_CIDR is 0.
31. Parallel Input/Output Controller (PIO) 31.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface.
31.3 Block Diagram Figure 31-1. Block Diagram PIODCCLK Data PDC Status PIODC[7:0] Parallel Capture Mode PIODCEN1 PIODCEN2 Interrupt Controller PMC PIO Interrupt PIO Clock PIO Controller Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Up to 32 peripheral IOs Embedded Peripheral PIN 31 APB Table 31-1.
Figure 31-2.
31.4 Product Dependencies 31.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e.
31.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 31-3. In this description each signal shown represents one of up to 32 possible indexes. Figure 31-3.
31.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status register (PIO_PUSR).
31.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR).
Figure 31-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 31.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled. Figure 31-5. Input Glitch Filter Timing PIO_IFCSR = 0 MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 Figure 31-6. 1 cycle up to 2.
Low-level detection High-level detection In order to select an additional interrupt mode: The type of event detection (edge or level) must be selected by writing in the Edge Select register (PIO_ESR) and Level Select register (PIO_LSR) which , respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).
Any edge on the other lines the configuration required is described below. 31.5.10.2 Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 31.5.10.3 Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
31.5.13 Parallel Capture Mode 31.5.13.1 Overview The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc. For better understanding and to ease reading, the following description uses an example with a CMOS digital image sensor. 31.5.13.
The flags DRDY, OVRE, ENDRX and RXBUFF can be a source of the PIO interrupt. Figure 31-10. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 0) MCK PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x5645_3423 RDATA (PIO_PCRHR) Figure 31-11.
Figure 31-12. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=0) MCK PIODCCLK PIODC[7:0] 0x12 0x01 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x6745_2301 RDATA (PIO_PCRHR) Figure 31-13. Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=1) MCK PIODCCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR RDATA (PIO_PCRHR) 0x7856_3412 31.5.13.
6. Read the data in PIO_PCRHR. 7. If new data are expected, go to step 4. 8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture mode WITHOUT changing the previous configuration. With PDC 1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode interrupt mask. 2. Configure PDC transfer in PDC registers. 3.
31.5.14 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the “PIO Write Protection Mode Register” (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “PIO Write Protection Status Register” (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
31.6 I/O Lines Programming Example The programming example shown in Table 31-2 is used to obtain the following configuration.
31.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 31-3.
Table 31-3.
Table 31-3.
31.7.1 PIO Enable Register Name: PIO_PER Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
31.7.3 PIO Status Register Name: PIO_PSR Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
31.7.4 PIO Output Enable Register Name: PIO_OER Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
31.7.6 PIO Output Status Register Name: PIO_OSR Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output.
31.7.
31.7.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line.
31.7.10 PIO Set Output Data Register Name: PIO_SODR Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. 31.7.
31.7.12 PIO Output Data Status Register Name: PIO_ODSR Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC) Access: Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0.
31.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1.
31.7.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0: No effect.
31.7.16 PIO Interrupt Mask Register Name: PIO_IMR Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0: Input Change interrupt is disabled on the I/O line.
31.7.
31.7.
31.7.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi-Drive Status 0: The multi-drive is disabled on the I/O line.
31.7.21 PIO Pull-Up Disable Register Name: PIO_PUDR Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
31.7.23 PIO Pull-Up Status Register Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line.
31.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
31.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Peripheral Select.
31.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select 0: No effect.
31.7.
31.7.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – 7 6 2 1 0 DIV 5 4 3 DIV • DIV: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
31.7.
31.7.
31.7.
31.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line.
31.7.36 PIO Additional Interrupt Modes Enable Register Name: PIO_AIMER Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Enable 0: No effect.
31.7.38 PIO Additional Interrupt Modes Mask Register Name: PIO_AIMMR Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral CD Status 0: The interrupt source is a both-edge detection event.
31.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection 0: No effect. 1: The interrupt source is an edge-detection event. 31.7.
31.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt Source Selection 0: The interrupt source is an edge-detection event.
31.7.43 PIO Rising Edge/High-Level Select Register Name: PIO_REHLSR Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High-Level Interrupt Selection 0: No effect.
31.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status 0: The I/O line is not locked. 1: The I/O line is locked.
31.7.46 PIO Write Protection Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC) Access: Read/Write Reset: See Table 31-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 5 – – 4 – – – For more information on write-protecting registers, refer to Section 31.5.14 ”Register Write Protection”.
31.7.47 PIO Write Protection Status Register Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC) Access: Read-only Reset: See Table 31-3 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR register.
31.7.
31.7.49 PIO Parallel Capture Mode Register Name: PIO_PCMR Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – FRSTS HALFS ALWYS – 7 6 5 – – 4 DSIZE 3 2 1 0 – – – PCEN This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” .
31.7.
31.7.
31.7.
31.7.53 PIO Parallel Capture Interrupt Status Register Name: PIO_PCISR Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – RXBUFF ENDRX OVRE DRDY • DRDY: Parallel Capture Mode Data Ready 0: No new data is ready to be read since the last read of PIO_PCRHR.
31.7.54 PIO Parallel Capture Reception Holding Register Name: PIO_PCRHR Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDATA 23 22 21 20 RDATA 15 14 13 12 RDATA 7 6 5 4 RDATA • RDATA: Parallel Capture Mode Reception Data. if DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful. if DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful.
32. Synchronous Serial Controller (SSC) 32.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
32.3 Block Diagram Figure 32-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 32.4 Application Block Diagram Figure 32-2.
32.5 Pin Name List Table 32-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 32.6 Type Product Dependencies 32.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
32.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 32.7.1.1 Clock Divider Figure 32-4.
32.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register.
Figure 32-7. Receiver Clock Management RK (pin) MUX Tri_state Controller Clock Output Transmitter Clock Divider Clock CKO CKS 32.7.1.4 Data Transfer INV MUX Tri_state Controller CKI CKG Receiver Clock Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers.
Figure 32-8. Transmitter Block Diagram SSC_CRTXEN TXEN SSC_SRTXEN SSC_CRTXDIS SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_RCMR.START SSC_TCMR.START SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.MSBF RXEN TXEN TX Start TX Start Start RX Start Start RF Selector Selector RF RC0R TX Controller TD Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY != 0 SSC_TFMR.DATLEN 0 SSC_THR Transmitter Clock 1 SSC_TSHR SSC_TFMR.FSLEN TX Controller counter reached STTDLY 32.7.
Figure 32-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start Start Selector RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR load SSC_RFMR.FSLEN Receiver Clock SSC_RHR SSC_RFMR.DATLEN RX Controller counter reached STTDLY 32.7.
Figure 32-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) TD (Output) B1 STTDLY BO X B1 STTDLY TD Start = Level Change on TF (Output) Start = Any Edge on TF BO BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 32-11.
32.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
32.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: the event that starts the data transfer (START) the delay in number of bit periods between the start event and the first data bit (STTDLY) the length of the data (DATLEN) the number of data to be transferred for each start event (DATNB).
Table 32-4.
Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 32-15. Receive Frame Format in Continuous Mode Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD Note: 1. STTDLY is set to 0. 32.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR.
32.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 32-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 32-18.
Figure 32-19.
32.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
32.9 Synchronous Serial Controller (SSC) User Interface Table 32-5.
32.9.1 SSC Control Register Name: SSC_CR: Address: 0x40004000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
32.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0x40004004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
32.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0x40004010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKG: Receive Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_RF_LOW Receive Clock enabled only if RF Low 2 EN_RF_HIGH Receive Clock enabled only if RF High • START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
32.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0x40004014 Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Receive Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN
32.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0x40004018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data 1 RECEIVE Receive start 2 TF_LOW Detection of a low level on TF signal 3 TF_HIGH Detection of a high level on TF signal 4 TF_FALLING Detection of a falling edge on TF signal 5 TF_RISING Detection of a rising edge on TF signal 6 TF_LEVEL Detection of any level chang
32.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0x4000401C Access: Read-write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Transmit Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer 4 HIGH Driven High during data transfer 5 TOGGLING Toggling at each start of data transfer • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
32.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0x40004020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
32.9.8 SSC Transmit Holding Register Name: SSC_THR Address: 0x40004024 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
32.9.
32.9.
32.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0x40004038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
32.9.12 SSC Receive Compare 1 Register Name: SSC_RC1R Address: 0x4000403C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
32.9.13 SSC Status Register Name: SSC_SR Address: 0x40004040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register.
32.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0x40004044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect.
• RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.
32.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0x40004048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect.
• RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.
32.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0x4000404C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled.
32.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0x400040E4 Access: Read-write Reset: See Table 32-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
32.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0x400040E8 Access: Read-only Reset: See Table 32-5 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
33. Serial Peripheral Interface (SPI) 33.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a Shift register that serially transmits data bits to other SPIs.
33.
33.3 Block Diagram Figure 33-1. Block Diagram AHB Matrix PDC Bus clock Peripheral bridge PMC Peripheral clock Trig.
33.4 Application Block Diagram Figure 33-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 MISO NC Slave 1 MOSI NPCS3 NSS SPCK MISO Slave 2 MOSI NSS 33.5 Signal Description Table 33-1.
Table 33-2. I/O Lines SPI NPCS0 PA11 A SPI NPCS1 PA9 B SPI NPCS1 PA31 A SPI NPCS1 PB14 A SPI NPCS1 PC4 B SPI NPCS2 PA10 B SPI NPCS2 PA30 B SPI NPCS2 PB2 B SPI NPCS3 PA3 B SPI NPCS3 PA5 B SPI NPCS3 PA22 B SPI SPCK PA14 A 33.6.2 Power Management The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 33.6.
The pins NPCS0 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master mode. 33.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit.
Figure 33-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 7 6 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined. 33.7.3 Master Mode Operations When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud rate generator.
If SPI_RDR has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 33-5, shows a block diagram of the SPI when operating in Master mode. Figure 33-6 on page 660 shows a flow chart describing how transfers are handled. 33.7.3.1 Master Mode Block Diagram Figure 33-5.
33.7.3.2 Master Mode Flow Diagram Figure 33-6.
Figure 33-7 shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags within SPI_SR during an 8-bit data transfer in Fixed mode without the Peripheral Data Controller involved. Figure 33-7.
Figure 33-8. PDC Status Register Flags Behavior 1 3 2 SPCK NPCS0 MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB TDRE (not required if PDC is used) PDC loads first byte PDC loads 2nd byte (double buffer effect) PDC loads last byte ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 33.7.3.
Figure 33-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS 33.7.3.5 DLYBS DLYBCT DLYBCT Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS signals are high before and after each transfer. Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral. Fixed peripheral select mode is enabled by writing the PS bit to zero in SPI_MR.
Transfer Size Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer size it has to point to. The PDC performs the following transfer, depending on the mode and number of bits per data. 33.7.3.7 Fixed mode: 8-bit data: 1-Byte transfer, PDC pointer address = address + 1 byte, PDC counter = counter - 1 8-bit to 16-bit data: 2-Byte transfer.
Figure 33-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI SPCK MISO MOSI Slave 0 Slave 1 Slave 14 NSS NSS SPI Master NSS NPCS0 NPCS1 NPCS2 NPCS3 Decoded chip select lines External 1-of-n Decoder/Demultiplexer 33.7.3.
asserted systematically during a time “DLYBCS” (the value of the CSNAAT bit is taken into account only if the CSAAT bit is set to 0 for the same chip select). Figure 33-11 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits. Figure 33-11. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..n] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..
external master on the NPCS0/NSS signal. In multi-master environment, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the MODF bit in SPI_SR is set until SPI_SR is read and the SPI is automatically disabled until it is re-enabled by writing the SPIEN bit in SPI_CR to 1. By default, the mode fault detection is enabled. The user can disable it by setting the MODFDIS bit in SPI_MR. 33.7.
33.7.5 Register Write Protection To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the ”SPI Write Protection Mode Register” (SPI_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the ”SPI Write Protection Status Register” (SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been attempted.
33.8 Serial Peripheral Interface (SPI) User Interface Table 33-5.
33.8.1 SPI Control Register Name: SPI_CR Address: 0x40008000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI.
33.8.2 SPI Mode Register Name: SPI_MR Address: 0x40008004 Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode.
LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on MOSI). PCS: Peripheral Chip Select This field is only used if fixed peripheral select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS.
33.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40008008 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD RD: Receive Data Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.
33.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4000800C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
33.8.5 SPI Status Register Name: SPI_SR Address: 0x40008010 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – SPIENS 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full 0: No data has been received since the last read of SPI_RDR.
0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. NSSR: NSS Rising 0: No rising edge detected on NSS pin since the last read. 1: A rising edge occurred on NSS pin since the last read. TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay.
33.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40008014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Enables the corresponding interrupt.
33.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40008018 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: No effect. 1: Disables the corresponding interrupt.
33.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4000801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
33.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0x40008030 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the default reset values.
BITS: Bits Per Transfer (See the note below the register table; Section 33.8.9 “SPI Chip Select Register” on page 680.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.
33.8.10 SPI Write Protection Mode Register Name: SPI_WPMR Address: 0x400080E4 Access: Read/Write Reset: See Table 33-5. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN WPEN: Write Protection Enable 0: Disables the Write Protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII) See Section 33.7.
33.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400080E8 Access: Read-only Reset: See Table 33-5 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of SPI_WPSR.
34. Two-wire Interface (TWI) 34.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
34.3 List of Abbreviations Table 34-2. 34.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 34-1.
34.5 Application Block Diagram Figure 34-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 34.5.1 I/O Lines Description Table 34-3. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 34.6 Type Product Dependencies 34.6.
34.6.3 Interrupt The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TWI. Table 34-5.
34.7 Functional Description 34.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 34-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 34-3). A high-to-low transition on the TWD line while TWCK is high defines the START condition.
34.8 Master Mode 34.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 34.8.2 Application Block Diagram Figure 34-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull-up value as given by the I²C Standard 34.8.
Figure 34-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 34-7.
Figure 34-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 34.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device.
Figure 34-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) NA P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 34.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 34.8.
Figure 34-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR P Figure 34-12.
34.8.7.2 4. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt. 5. Disable the PDC by setting the PDC TXTDIS bit. 6. Wait for the TXRDY flag in TWI_SR. 7. Set the STOP command in TWI_CR. 8. Write the last character in TWI_THR. 9. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required. Data Receive with the PDC The PDC transfer size must be defined with the buffer size minus 2.
Figure 34-15.
Figure 34-16.
Figure 34-17.
Figure 34-18.
Figure 34-19.
Figure 34-20.
34.9 Multi-master Mode 34.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 34-21. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 34-22.
Figure 34-23.
34.10 Slave Mode 34.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 34.10.2 Application Block Diagram Figure 34-24.
34.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 34-26 on page 707. 34.10.4.
34.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
34.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded.
Figure 34-29. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full S TWD SADR W A DATA0 A DATA1 TWI_RHR A NA DATA2 DATA1 DATA0 is not read in the RHR S ADR DATA2 SCLWS SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD As soon as a START is detected TXCOMP Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2.
Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 34-31 describes the repeated start + reversal from Write to Read mode. Figure 34-31. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 A DATA0 Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP Read TWI_RHR Cleared after read As soon as a START is detected Notes: 1.
34.10.7 Read Write Flowcharts The flowchart shown in Figure 34-32 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 34-32.
34.11 Two-wire Interface (TWI) User Interface Table 34-7.
34.11.1 TWI Control Register Name: TWI_CR Address: 0x40018000 (0), 0x4001C000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0: No effect. 1: If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset.
34.11.
34.11.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x40018008 (0), 0x4001C008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
34.11.4 TWI Internal Address Register Name: TWI_IADR Address: 0x4001800C (0), 0x4001C00C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
34.11.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x40018010 (0), 0x4001C010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
34.11.6 TWI Status Register Name: TWI_SR Address: 0x40018020 (0), 0x4001C020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 34-25 on page 706, Figure 34-28 on page 708, Figure 34-30 on page 709 and Figure 34-31 on page 710. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode.
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
34.11.7 TWI Interrupt Enable Register Name: TWI_IER Address: 0x40018024 (0), 0x4001C024 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect.
34.11.8 TWI Interrupt Disable Register Name: TWI_IDR Address: 0x40018028 (0), 0x4001C028 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: No effect.
34.11.9 TWI Interrupt Mask Register Name: TWI_IMR Address: 0x4001802C (0), 0x4001C02C (1) Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
34.11.
34.11.
35. Universal Asynchronous Receiver Transmitter (UART) 35.1 Description The Universal Asynchronous Receiver Transmitter (UART) features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with a peripheral DMA controller (PDC) permits packet handling for these tasks with processor time reduced to a minimum. 35.2 Embedded Characteristics 35.
35.4 Product Dependencies 35.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 35-2. I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PA9 A UART0 UTXD0 PA10 A UART1 URXD1 PB2 A UART1 UTXD1 PB3 A 35.4.2 Power Management The UART clock can be controlled through the Power Management Controller (PMC).
Figure 35-2. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 Divide by 16 1 Baud Rate Clock 0 0 Receiver Sampling Clock 35.5.2 Receiver 35.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the Control register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
Figure 35-4. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling 35.5.2.3 D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit Receiver Ready When a complete character is received, it is transferred to the Receive Holding register (UART_RHR) and the RXRDY status bit in the Status register (UART_SR) is set. The bit RXRDY is automatically cleared when UART_RHR is read. Figure 35-5.
Figure 35-7. Parity Error S URXD D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit 35.5.2.6 RSTSTA Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1.
Figure 35-9. Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit 35.5.3.3 D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts when the programmer writes in the Transmit Holding register (UART_THR), and after the written character is transferred from UART_THR to the Shift Register.
The local loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and the UTXD line is held high, as in idle state. The remote loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 35-11.
35.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 35-3.
35.6.1 UART Control Register Name: UART_CR Address: 0x400E0600 (0), 0x400E0800 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
35.6.
35.6.3 UART Interrupt Enable Register Name: UART_IER Address: 0x400E0608 (0), 0x400E0808 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
35.6.4 UART Interrupt Disable Register Name: UART_IDR Address: 0x400E060C (0), 0x400E080C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
35.6.5 UART Interrupt Mask Register Name: UART_IMR Address: 0x400E0610 (0), 0x400E0810 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
35.6.6 UART Status Register Name: UART_SR Address: 0x400E0614 (0), 0x400E0814 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0: No character has been received since the last read of the UART_RHR, or the receiver is disabled.
• TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active.
35.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0x400E0618 (0), 0x400E0818 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
35.6.8 UART Transmit Holding Register Name: UART_THR Address: 0x400E061C (0), 0x400E081C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
35.6.
36. Universal Synchronous Asynchronous Receiver Transceiver (USART) 36.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
36.3 Block Diagram Figure 36-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS DTR PMC Modem Signals Control MCK DIV DSR DCD MCK/DIV RI SLCK SCK Baud Rate Generator User Interface APB Table 36-1.
36.4 Application Block Diagram Figure 36-2.
36.5 I/O Lines Description Table 36-2.
36.6 Product Dependencies 36.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
36.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART Table 36-4. Peripheral IDs Instance ID USART0 14 USART1 15 interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
36.7 Functional Description 36.7.1 Baud Rate Generator The baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter.
Table 36-5 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 36-5. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (Bit/s) Calculation Result CD Actual Baud Rate (Bit/s) Error 3,686,400 38,400 6.00 6 38,400.00 0.00% 4,915,200 38,400 8.00 8 38,400.00 0.00% 5,000,000 38,400 8.14 8 39,062.50 1.70% 7,372,800 38,400 12.00 12 38,400.00 0.
Figure 36-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 Glitch-free Logic 3 FIDI >1 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 36.7.1.3 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in the US_BRGR.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-7. Table 36-7. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 36-8 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 36-8.
The receiver and the transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset.
Figure 36-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 36.7.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1.
Figure 36-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register.
Figure 36-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 36-12 and Figure 36-13 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 36-12.
The RXIDLEV bit in the US_MAN informs the USART of the receiver line idle state value (receiver line inactive). The user must define RXIDLEV to ensure reliable synchronization. By default, RXIDLEV is set to one (receiver line is at level 1 when there is no activity). Figure 36-14.
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.
Figure 36-18. ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 36-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 36.7.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock.
Figure 36-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 36.7.3.8 Parity The USART supports five parity modes that are selected by writing to the PAR field in the US_MR. The PAR field also enables the multidrop mode, see “Multidrop Mode” on page 764. Even and odd parity bit generation and error detection are supported.
Figure 36-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE Parity Error Detect Time Flags Report Time RXRDY 36.7.3.9 Multidrop Mode If the value 0x6 or 0x07 is written to the PAR field in the US_MR, the USART runs in multidrop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1.
Figure 36-23. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 36-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 36-10. Maximum Timeguard Length Depending on Baud Rate Baud Rate (Bit/s) Bit Time (µs) Timeguard (ms) 1,200 833 212.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO.
Figure 36-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 36.7.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits to 0.
Figure 36-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 36.7.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR.
Figure 36-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 36-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 36-29.
transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. 36.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in US_CSR. If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing US_CR with the RSTIT bit to 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the US_MR.
36.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kb/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 36-12. Table 36-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 36-34 shows an example of character transmission. Figure 36-34.
Table 36-13. IrDA Baud Rate Error (Continued) Peripheral Clock 36.7.5.3 Baud Rate (Bit/s) CD Baud Rate Error Pulse Time (µs) 32,768,000 19,200 107 0.31% 9.77 40,000,000 19,200 130 0.16% 9.77 3,686,400 9,600 24 0.00% 19.53 20,000,000 9,600 130 0.16% 19.53 32,768,000 9,600 213 0.16% 19.53 40,000,000 9,600 260 0.16% 19.53 3,686,400 2,400 96 0.00% 78.13 20,000,000 2,400 521 0.03% 78.13 32,768,000 2,400 853 0.04% 78.
Figure 36-36. Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS The USART is set in RS485 mode by writing the value 0x1 to the USART_MODE field in US_MR. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 36-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 36-37.
36.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in US_MR to the value 0x3.
36.7.8 SPI Mode The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with external devices in master or slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
36.7.8.3 The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin. To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least 6 times lower than the system clock.
Figure 36-39. SPI Transfer Format (CPHA = 0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 8 7 6 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 36.7.8.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 754. 36.7.8.
36.7.8.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in the Status register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a one to the RSTSTA (Reset Status) bit the US_CR.
Figure 36-42. Local Loopback Mode Configuration RXD Receiver 1 Transmitter 36.7.9.4 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 36-43. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 36-43.
36.7.10 Register Write Protection To prevent any single software error from corrupting USART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “USART Write Protection Mode Register” (US_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “USART Write Protection Status Register” (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
36.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 36-16.
36.8.1 USART Control Register Name: US_CR Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 786. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
• RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.
36.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 788. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver.
• FCS: Force SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Releases the Slave Select Line NSS (RTS pin).
36.8.3 USART Mode Register Name: US_MR Address: 0x40024004 (0), 0x40028004 (1) Access: Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817.
• CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in asynchronous mode. 1: USART operates in synchronous mode.
• MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.
• ONEBIT: Start Frame Delimiter Selector 0: Start frame delimiter is COMMAND or DATA SYNC. 1: Start frame delimiter is one bit.
36.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0x40024004 (0), 0x40028004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 – 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 788.
• CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic echo mode. Receiver input is connected to the TXD pin. Local loopback mode. Transmitter output is connected to the Receiver Input. Remote loopback mode. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero.
36.8.5 USART Interrupt Enable Register Name: US_IER Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 796.
• DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 795
36.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 788.
36.8.7 USART Interrupt Disable Register Name: US_IDR Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 799.
• DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 798
36.8.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 788.
36.8.9 USART Interrupt Mask Register Name: US_IMR Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 802.
• DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 801
36.8.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 788.
36.8.11 USART Channel Status Register Name: US_CSR Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 806.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• RI: Image of RI Input 0: RI is set to 0. 1: RI is set to 1. • DSR: Image of DSR Input 0: DSR is set to 0 1: DSR is set to 1. • DCD: Image of DCD Input 0: DCD is set to 0. 1: DCD is set to 1. • CTS: Image of CTS Input 0: CTS is set to 0. 1: CTS is set to 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.
36.8.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 788.
36.8.13 USART Receive Holding Register Name: US_RHR Address: 0x40024018 (0), 0x40028018 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last character received is a data. 1: Last character received is a command.
36.8.14 USART Transmit Holding Register Name: US_THR Address: 0x4002401C (0), 0x4002801C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data.
36.8.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0x40024020 (0), 0x40028020 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817.
36.8.16 USART Receiver Time-out Register Name: US_RTOR Address: 0x40024024 (0), 0x40028024 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817. • TO: Time-out Value 0: The receiver time-out is disabled.
36.8.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x40024028 (0), 0x40028028 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817. • TG: Timeguard Value 0: The transmitter timeguard is disabled.
36.8.18 USART FI DI RATIO Register Name: US_FIDI Address: 0x40024040 (0), 0x40028040 (1) Access: Read/Write Reset: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817.
36.8.19 USART Number of Errors Register Name: US_NER Address: 0x40024044 (0), 0x40028044 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in “USART Mode Register” on page 788. • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer.
36.8.20 USART IrDA FILTER Register Name: US_IF Address: 0x4002404C (0), 0x4002804C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in “USART Mode Register” on page 788. This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817.
36.8.21 USART Manchester Configuration Register Name: US_MAN Address: 0x40024050 (0), 0x40028050 (1) Access: Read/Write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 817.
• RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.
36.8.22 USART Write Protection Mode Register Name: US_WPMR Address: 0x400240E4 (0), 0x400280E4 (1) Access: Read/Write Reset: See Table 36-16 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
36.8.23 USART Write Protection Status Register Name: US_WPSR Address: 0x400240E8 (0), 0x400280E8 (1) Access: Read-only Reset: See Table 36-16 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the US_WPSR.
37. Timer Counter (TC) 37.1 Description The Timer Counter (TC) includes 3 identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
37.3 Two global registers that act on all TC channels Compare event fault generation for PWM Register Write Protection Block Diagram Figure 37-1.
37.4 Pin Name List Table 37-3. 37.5 TC pin list Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O Product Dependencies 37.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 37-4.
37.5.4 Fault Output The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 37.6.17 “Fault Mode” and to the product Pulse Width Modulation (PWM) implementation. 37.6 Functional Description 37.6.1 TC Description The 3 channels of the Timer Counter are independent and identical in operation except when quadrature decoder is enabled. The registers for channel programming are listed in Table 37-5 “Register Mapping”. 37.6.
Figure 37-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 37-3.
37.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 37-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR). In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in the TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
• Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in the TC_CMR.
MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST MCK Synchronous Edge Detection R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT
37.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TIOB
37.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 37-8. RC Compare cannot be programmed to generate a trigger in this configuration.
37.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 37-10.
37.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 is reached, the value of TC_CV is decremented to 0, then re-incremented to 216-1 and so on. See Figure 37-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-12.
37.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 37-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-14.
37.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
Figure 37-15. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA0 QDEN PHEdges TIOA0 TIOB0 TIOB1 1 TIOB0 TIOB 1 XC0 XC0 PHA Speed/Position QDEN PHB IDX Timer/Counter Channel 0 TIOA Index 1 TIOB1 TIOB 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 37.6.14.
Figure 37-16. Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter FILTER PHedge 1 TIOA0 Direction and Edge Detection INVA 1 PHB Filter 1 DIR Filter 1 IDX TIOB0 INVB 1 1 IDX TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference.
Figure 37-17.
37.6.14.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
Figure 37-19. Quadrature Error Detection MAXFILT = 2 MCK Abnormally formatted optical disk strips (theoretical view) PHA PHB strip edge inaccurary due to disk etching/printing process PHA PHB resulting PHA, PHB electrical waveforms PHA Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA output. This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set. Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0).
37.6.17 Fault Mode At anytime, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value (TC_CVx) with the value of TC_RCx register. The CPCSx flags can be set accordingly and an interrupt can be generated. This interrupt is processed but requires an unpredictable amount of time to be achieve the required action. It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1.
37.7 Timer Counter (TC) User Interface Table 37-5.
37.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: (1)[2] 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1.
37.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal.
37.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVE = 1) Access: Read/Write 31 30 29 BSWTRG 23 28 27 BEEVT 22 21 ASWTRG 20 19 AEEVT 15 WAVE 14 13 7 CPCDIS 6 CPCSTOP WAVSEL 26 25 24 BCPC BCPB 18 17 16 ACPC 12 ENETRG 11 4 3 CLKI 5 BURST ACPA 10 9 EEVT 8 EEVTEDG 2 1 TCCLKS 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event.
• ACPA: RA Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
• BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 848
37.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..2] Address: (1)[2] 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1], 0x40014088 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 DOWN 0 GCEN This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
37.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Address: (1)[2] 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
37.7.6 TC Register A Name: TC_RAx [x=0..2] Address: (1)[2] 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1], 0x40014094 Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
37.7.7 TC Register B Name: TC_RBx [x=0..2] Address: (1)[2] 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1], 0x40014098 Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
37.7.8 TC Register C Name: TC_RCx [x=0..2] Address: (1)[2] 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1], 0x4001409C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RC: Register C RC contains the Register C value in real time.
37.7.9 TC Status Register Name: TC_SRx [x=0..
• ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high.
37.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: (1)[2] 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140A4 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt.
37.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: (1)[2] 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140A8 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt.
37.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: (1)[2] 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1], 0x400140AC Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled.
37.7.13 TC Block Control Register Name: TC_BCR Address: 0x400100C0 (0), 0x400140C0 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
37.7.14 TC Block Mode Register Name: TC_BMR Address: 0x400100C4 (0), 0x400140C4 (1) Access: Read/Write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 25 21 20 19 FILTER 18 – 17 IDXPHB 16 SWAP MAXFILT 24 MAXFILT 15 INVIDX 14 INVB 13 INVA 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 7 – 6 – 5 4 3 2 1 0 TC2XC2S TC1XC1S TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
Quadrature decoding (direction change) can be disabled using QDTRANS bit. One of the POSEN or SPEEDEN bits must be also enabled. • POSEN: POSition ENabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. • SPEEDEN: SPEED ENabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding TRANSparent 0: Full quadrature decoding logic is active (direction change detected).
37.7.15 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400100C8 (0), 0x400140C8 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0: No effect.
37.7.16 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400100CC (0), 0x400140CC (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0: No effect.
37.7.17 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400100D0 (0), 0x400140D0 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. • DIRCHG: DIRection CHanGe 0: The interrupt on rotation direction change is disabled.
37.7.18 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400100D4 (0), 0x400140D4 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: InDeX 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR.
37.7.19 TC Fault Mode Register Name: TC_FMR Address: 0x400100D8 (0), 0x400140D8 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 ENCF1 0 ENCF0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • ENCF0: ENable Compare Fault Channel 0 0: Disables the FAULT output source (CPCS flag) from channel 0.
37.7.20 TC Write Protection Mode Register Name: TC_WPMR Address: 0x400100E4 (0), 0x400140E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). See Section 37.6.
38. High Speed MultiMedia Card Interface (HSMCI) 38.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
38.3 Block Diagram Figure 38-1. Block Diagram (4-bit configuration) APB Bridge PDC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.
38.4 Application Block Diagram Figure 38-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 SDCard MMC 38.5 Pin Name List Table 38-1. I/O Lines Description for 4-bit Configuration Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..
38.6 Product Dependencies 38.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 38-2. I/O Lines Instance Signal I/O Line Peripheral HSMCI MCCDA PA28 C HSMCI MCCK PA29 C HSMCI MCDA0 PA30 C HSMCI MCDA1 PA31 C HSMCI MCDA2 PA26 C HSMCI MCDA3 PA27 C 38.6.
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 38-4.
Figure 38-5. SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 38-5. Table 38-5.
38.8 High Speed MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol. Each message is represented by one of the following tokens: Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 38-6 and Table 38-7. Table 38-6. ALL_SEND_CID Command Description CMD Index Type Argument Response Abbreviation Command Description CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: 1. Table 38-7. bcr means broadcast command with response.
Figure 38-7. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: 1.
38.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in HSMCI_MR, then all reads and writes use the PDC facilities.
Figure 38-8.
38.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart (Figure 38-9) shows how to write a single block with or without use of PDC facilities.
Figure 38-9.
The following flowchart (Figure 38-10) shows how to manage a multiple write block transfer with the PDC. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR). Figure 38-10.
38.9 SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
38.10 CE-ATA Operation CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands: GO_IDLE_STATE (CMD0): used for hard reset. STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted. FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access only.
register, no error recovery action is required. The ATA command itself failed implying that the device could not complete the action requested, however, there was no communication or protocol failure. After the device signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command. 38.
38.12.3 Write Access During a write access, the XFRDONE flag behaves as shown in Figure 38-12. Figure 38-12. XFRDONE During a Write Access CMD line HSMCI write CMD CMDRDY flag Card response The CMDRDY flag is released 8 tbit after the end of the card response.
38.13 Register Write Protection To prevent any single software error from corrupting HSMCI behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “HSMCI Write Protection Mode Register” (HSMCI_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the “HSMCI Write Protection Status Register” (HSMCI_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 38-8.
38.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0x40000000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0: No effect. 1: Disables the Multi-Media Interface.
38.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0x40000004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 PDCMODE 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 912.
• PDCMODE: PDC-oriented Mode 0: Disables PDC transfer 1: Enables PDC transfer. In this case, UNRE and OVRE flags in the HSMCI Status Register (HSMCI_SR) are deactivated after the PDC transfer has been completed.
38.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0x40000008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 912.
38.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0x4000000C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 912. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
38.14.
38.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0x40000014 Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD).
• OPDCMD: Open Drain Command 0 (PUSHPULL): Push pull command. 1 (OPENDRAIN): Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5): 5-cycle max latency. 1 (64): 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DAT A Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE): Write. 1 (READ): Read.
38.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0x40000018 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Command Register (HSMCI_CMDR).
38.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0x4000001C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 912.
38.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0x40000020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
38.14.
38.14.
38.14.12HSMCI Status Register Name: HSMCI_SR Address: 0x40000040 Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block. The NOTBUSY flag allows to deal with these different states. 0: The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 1: The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended.
• RDIRE: Response Direction Error 0: No error. 1: The direction bit from card to host in the response has not been detected. • RCRCE: Response CRC Error 0: No error. 1: A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR. • RENDE: Response End Bit Error 0: No error. 1: The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR. • RTOE: Response Time-out Error 0: No error.
• OVRE: Overrun 0: No error. 1: At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read. • UNRE: Underrun 0: No error. 1: At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
38.14.13HSMCI Interrupt Enable Register Name: HSMCI_IER Address: 0x40000044 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
• RTOE: Response Time-out Error Interrupt Enable • DCRCE: Data CRC Error Interrupt Enable • DTOE: Data Time-out Error Interrupt Enable • CSTOE: Completion Signal Timeout Error Interrupt Enable • FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 906
38.14.14HSMCI Interrupt Disable Register Name: HSMCI_IDR Address: 0x40000048 Access: Write-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 – 24 – 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 TXBUFE 14 RXBUFF 13 CSRCV 12 SDIOWAIT 11 – 10 – 9 – 8 SDIOIRQA 7 ENDTX 6 ENDRX 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY The following configuration values are valid for all listed bit names of this register: 0: No effect.
• RTOE: Response Time-out Error Interrupt Disable • DCRCE: Data CRC Error Interrupt Disable • DTOE: Data Time-out Error Interrupt Disable • CSTOE: Completion Signal Time out Error Interrupt Disable • FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 908
38.14.
• RTOE: Response Time-out Error Interrupt Mask • DCRCE: Data CRC Error Interrupt Mask • DTOE: Data Time-out Error Interrupt Mask • CSTOE: Completion Signal Time-out Error Interrupt Mask • FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 910
38.14.16HSMCI Configuration Register Name: HSMCI_CFG Address: 0x40000054 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 912.
38.14.17HSMCI Write Protection Mode Register Name: HSMCI_WPMR Address: 0x400000E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII). See Section 38.
38.14.18HSMCI Write Protection Status Register Name: HSMCI_WPSR Address: 0x400000E8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the HSMCI_WPSR. 1: A Write Protect Violation has occurred since the last read of the HSMCI_WPSR.
39. Pulse Width Modulation Controller (PWM) 39.1 Description The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator.
2 Independent Events Lines Intended to Synchronize ADC Conversions Programmable delay for Events Lines to delay ADC measurements 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and PDC Transfer Requests 8 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs 39.
39.4 I/O Lines Description Each channel outputs two complementary external I/O lines. Table 39-1.
39.5 Product Dependencies 39.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 39-2.
Table 39-2. I/O Lines PWM PWML1 PC15 B PWM PWML2 PA16 C PWM PWML2 PA30 A PWM PWML2 PB13 A PWM PWML2 PC2 B PWM PWML3 PA15 C PWM PWML3 PC3 B PWM PWML3 PC22 B 39.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later.
39.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. Clocked by the master clock (MCK), the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 39.6.1 PWM Clock Generator Figure 39-2.
At reset, all clocks provided by the modulo n counter are turned off except clock “MCK”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. CAUTION: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). 39.6.2 PWM Channel 39.6.2.1 Channel Block Diagram Figure 39-3.
39.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM Channel Period Register” (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM Channel Duty Cycle Register” (PWM_CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are: the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator described in the previous section.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG bit of the PWM_CMRx. The default mode is left aligned. Figure 39-4. Non Overlapped Center Aligned Waveforms No overlap OC0 OC1 Period Note: 1. See Figure 39-5 on page 923 for a detailed description of center aligned waveforms. When center aligned, the channel counter increases up to CPRD and decreases down to 0.
Figure 39-5.
Figure 39-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 39.6.2.4 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely.
Figure 39-7. Complementary Output Waveforms output waveform OCx CPOLx = 0 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx output waveform OCx CPOLx = 1 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 39.6.2.
By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written. The value of the current output selection can be read in PWM_OS. While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined values. 39.6.2.6 Fault Protection 8 inputs provide fault protection which can force any of the PWM output pairs to a programmable value.
CAUTION: To prevent an unexpected activation of the status flag FSy in the PWM_FSR, the FMODy bit can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. If a comparison unit is enabled (see Section 39.6.
Table 39-5. Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous channels are written by the Peripheral DMA Controller (PDC) (see “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on page 930). The user can choose to synchronize the PDC transfer request with a comparison match (see Section 39.6.3 “PWM Comparison Units”), by the fields PTRM and PTRCS in the PWM_SCM register.
Figure 39-10. Method 1 (UPDM = 0) CCNT0 CDTYUPD 0x20 0x40 0x20 0x40 0x60 UPDULOCK CDTY 0x60 Method 2: Manual write of duty-cycle values and automatic trigger of the update In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update Period is elapsed. Go to Step 8. for new values. Figure 39-11.
Depending on the interrupt mask in the PWM_IMR2, an interrupt can be generated by these flags. Sequence for Method 3: 1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the PWM_SCM register. 2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register. 3. Define the update period by the field UPR in the PWM_SCUP register. 4.
Figure 39-13. Method 3 (UPDM=2 and PTRM=1 and PTRCS=0) CCNT0 CDTYUPD 0x20 UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x80 0xB0 0xA0 0x3 0x3 0x1 0x0 0x1 0x40 0x20 0x0 0x1 0x0 0x80 0x60 0x1 0x2 0x3 0x1 0x0 0x2 0xA0 CMP0 match transfer request WRDY 39.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 39.
comparison is made when the counter is counting up or counting down (in left alignment mode CALG = 0, this bit is useless). If a fault is active on the channel 0, the comparison is disabled and cannot match (see Section 39.6.2.6 “Fault Protection”). The user can define the periodicity of the comparison x by the fields CTR and CPR (in PWM_CMPVx).
Figure 39-15. Comparison Waveform CCNT0 CVUPD 0x6 0x6 0x2 CVMVUPD CTRUPD 0x1 0x2 CPRUPD 0x1 0x3 CUPRUPD 0x3 0x2 CV 0x6 0x2 CTR 0x1 0x2 CPR 0x1 0x3 CUPR 0x3 0x2 CUPRCNT 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 CPRCNT 0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x6 CVM Comparison Update CMPU Comparison Match CMPM 39.6.
39.6.5 PWM Controller Operations 39.6.5.1 Initialization Before enabling the channels, they must have been configured by the software application: 39.6.5.2 Unlock User Interface by writing the WPCMD field in the PWM_WPCR. Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).
If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit UPDULOCK is written at ‘1’ (in “PWM Sync Channels Update Control Register” (PWM_SCUC)) and the end of the current PWM period, then update the values for the next period.
Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is taken into account. Note: Changing the update period does make sense only if there is one or more synchronous channels and if the update method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ). Figure 39-18.
Figure 39-19. Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value Comparison Value for comparison x PWM_CMPMUPDx Value Comparison configuration for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of Comparison Update Period and and PWM_CMPMx written End of channel0 PWM period and end of Comparison Update Period 39.6.5.
Register group 4: “PWM Channel Dead Time Register” on page 986 “PWM Channel Dead Time Update Register” on page 987 Register group 5: “PWM Fault Mode Register” on page 965 “PWM Fault Protection Value Register” on page 968 There are two types of Write Protection: SW Write Protect—can be enabled or disabled by software HW Write Protect—can be enabled by software but only disabled by a hardware reset of the PWM controller Both types of Write Protect can be applied independently to
39.7 Pulse Width Modulation Controller (PWM) User Interface Table 39-6.
Table 39-6.
Table 39-6.
39.7.1 PWM Clock Register Name: PWM_CLK Address: 0x40020000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the “PWM Write Protection Status Register” .
39.7.2 PWM Enable Register Name: PWM_ENA Address: 0x40020004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x.
39.7.3 PWM Disable Register Name: PWM_DIS Address: 0x40020008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the “PWM Write Protection Status Register” . • CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x.
39.7.4 PWM Status Register Name: PWM_SR Address: 0x4002000C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled.
39.7.
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39.7.
39.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0x4002001C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x 0: No new counter event has occurred since the last read of the PWM_ISR1. 1: At least one counter event has occurred since the last read of the PWM_ISR1.
39.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0x40020020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 PTRCS 21 20 PTRM 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 16 UPDM This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the “PWM Write Protection Status Register” . • SYNCx: Synchronous Channel x 0: Channel x is not a synchronous channel.
39.7.
39.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0x4002002C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” ).
39.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0x40020030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
39.7.
39.7.
39.7.
39.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0x40020040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update 0: New duty-cycle and dead-time values for the synchronous channels cannot be written.
39.7.17 PWM Output Override Value Register Name: PWM_OOV Address: 0x40020044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 • OOVHx: Output Override Value for PWMH output of the channel x 0: Override value is 0 for PWMH output of channel x. 1: Override value is 1 for PWMH output of channel x.
39.7.18 PWM Output Selection Register Name: PWM_OS Address: 0x40020048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 • OSHx: Output Selection for PWMH output of the channel x 0: Dead-time generator output DTOHx selected as PWMH output of channel x. 1: Output override value OOVHx selected as PWMH output of channel x.
39.7.19 PWM Output Selection Set Register Name: PWM_OSS Address: 0x4002004C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 • OSSHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x.
39.7.20 PWM Output Selection Clear Register Name: PWM_OSC Address: 0x40020050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 • OSCHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x.
39.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0x40020054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 • OSSUPHx: Output Selection Set for PWMH output of the channel x 0: No effect.
39.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0x40020058 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 • OSCUPHx: Output Selection Clear for PWMH output of the channel x 0: No effect.
39.7.23 PWM Fault Mode Register Name: PWM_FMR Address: 0x4002005C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” . • FPOL: Fault Polarity For each field bit y (fault input number): 0: The fault y becomes active when the fault input y is at 0.
39.7.24 PWM Fault Status Register Name: PWM_FSR Address: 0x40020060 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV • FIV: Fault Input Value For each field bit y (fault input number): 0: The current sampled value of the fault input y is 0 (after filtering if enabled). 1: The current sampled value of the fault input y is 1 (after filtering if enabled).
39.7.25 PWM Fault Clear Register Name: PWM_FCR Address: 0x40020064 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR • FCLR: Fault Clear For each field bit y (fault input number): 0: No effect.
39.7.26 PWM Fault Protection Value Register Name: PWM_FPV Address: 0x40020068 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” .
39.7.27 PWM Fault Protection Enable Register Name: PWM_FPE Address: 0x4002006C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” . Only the first 8 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
39.7.28 PWM Event Line x Register Name: PWM_ELMRx Address: 0x4002007C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 • CSELy: Comparison y Selection 0: A pulse is not generated on the event line x when the comparison y matches. 1: A pulse is generated on the event line x when the comparison y match.
39.7.29 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0x400200B0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GCEN1 0 GCEN0 • GCENx: Gray Count ENable 0: Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1: enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
39.7.30 PWM Write Protection Control Register Name: PWM_WPCR Address: 0x400200E4 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 0 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct (0x50574D, “PWM” in ASCCII).
– “PWM Channel Period Register” on page 983 – “PWM Channel Period Update Register” on page 984 • Register group 4: – “PWM Channel Dead Time Register” on page 986 – “PWM Channel Dead Time Update Register” on page 987 • Register group 5: – “PWM Fault Mode Register” on page 965 – “PWM Fault Protection Value Register” on page 968 SAM4S Series [DATASHEET] 11100F–ATARM–29-Jan-14 973
39.7.31 PWM Write Protection Status Register Name: PWM_WPSR Address: 0x400200E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 • WPSWSx: Write Protect SW Status 0: The Write Protect SW x of the register group x is disabled. 1: The Write Protect SW x of the register group x is enabled.
39.7.32 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0x40020130 [0], 0x40020140 [1], 0x40020150 [2], 0x40020160 [3], 0x40020170 [4], 0x40020180 [5], 0x40020190 [6], 0x400201A0 [7] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant.
39.7.33 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5], 0x40020194 [6], 0x400201A4 [7] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
39.7.34 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0x40020138 [0], 0x40020148 [1], 0x40020158 [2], 0x40020168 [3], 0x40020178 [4], 0x40020188 [5], 0x40020198 [6], 0x400201A8 [7] Access: Read/Write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 24 – 17 16 9 8 1 – 0 CEN CUPR 12 11 10 CPRCNT 7 25 – CPR 5 4 CTR 3 – 2 – • CEN: Comparison x Enable 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match.
39.7.35 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0x4002013C [0], 0x4002014C [1], 0x4002015C [2], 0x4002016C [3], 0x4002017C [4], 0x4002018C [5], 0x4002019C [6], 0x400201AC [7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values.
39.7.36 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 – 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the “PWM Write Protection Status Register” .
• CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in “PWM Interrupt Status Register 1” ). CALG = 0 (Left Alignment): 0/1: The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0: The channel counter event occurs at the end of the PWM period. 1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
39.7.37 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
39.7.38 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3] Access: Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle.
39.7.39 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the “PWM Write Protection Status Register” . Only the first 16 bits (channel counter size) are significant.
39.7.40 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the “PWM Write Protection Status Register” . This register acts as a double buffer for the CPRD value.
39.7.41 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Address: 0x40020214 [0], 0x40020234 [1], 0x40020254 [2], 0x40020274 [3] Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value.
39.7.42 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Address: 0x40020218 [0], 0x40020238 [1], 0x40020258 [2], 0x40020278 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the “PWM Write Protection Status Register” . Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
39.7.43 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Address: 0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the “PWM Write Protection Status Register” . This register acts as a double buffer for the DTH and DTL values.
40. USB Device Port (UDP) 40.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) 2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
Block Diagram Figure 40-1. Block Diagram Atmel Bridge APB to MCU Bus txoen eopn Wrapper MCK USB Device UDPCK Dual Port RAM FIFO User Interface Serial Interface Engine Wrapper 40.3 12 MHz txd rxdm Embedded USB Transceiver DDP DDM rxd SIE rxdp udp_int (interrupt line) Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pull-up on DDP must be disabled in order to prevent feeding current to the host.
40.5 Typical Connection Figure 40-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 40.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. However, discrete components are required for each of the following actions: to monitor VBUS voltage for line termination to disconnect the host for reduced power consumption 40.5.
40.6 Functional Description 40.6.1 USB 2.0 Full-speed Introduction The USB 2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 40-3. Example of USB 2.0 Full-speed Communication Control USB Host V2.
40.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 40-5.
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 40.6.2 Handling Transactions with USB 2.0 Device Peripheral 40.6.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device.
4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx. 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx. 7.
Figure 40-7.
Figure 40-8.
Figure 40-9.
4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx. 7.
A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. 3.
40.6.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 40-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
40.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 40-14.
40.6.3.2 Entering Attached State To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pull-up connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 40.6.3.
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR and clearing TXVDIS in the UDP_TXVC register. 40.6.3.
40.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 40-6.
40.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Address: 0x40034000 Access: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
40.7.2 UDP Global State Register Name: UDP_GLB_STAT Address: 0x40034004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 RMWUPE 3 RSMINPR 2 ESR 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.
40.7.3 UDP Function Address Register Name: UDP_FADDR Address: 0x40034008 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
40.7.
40.7.
40.7.
WAKEUP: USB Bus WAKEUP Interrupt 0: USB Bus Wakeup Interrupt is disabled 1: USB Bus Wakeup Interrupt is enabled Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.
40.7.
RXRSM: UDP Resume Interrupt Status 0: No UDP Resume Interrupt pending 1: UDP Resume Interrupt has been raised The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR. SOFINT: Start of Frame Interrupt Status 0: No Start of Frame Interrupt pending 1: Start of Frame Interrupt has been raised This interrupt is raised each time a SOF token has been detected.
40.7.
40.7.
40.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK) Name: UDP_CSRx [x = 0..
/// Clears the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to clear to 0.
This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state 1: Stall state Write: 0: Return to normal state 1: Send STALL to the host Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
EPTYPE[2:0]: Endpoint Type Read/Write Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 5 ISO_IN Isochronous IN 2 BULK_OUT Bulk OUT 6 BULK_IN Bulk IN 3 INT_OUT Interrupt OUT 7 INT_IN Interrupt IN DTGLE: Data Toggle Read-only: 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
40.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS) Name: UDP_CSRx [x = 0..
RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device.
FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state. 1: Stall state. Write: 0: Return to normal state. 1: Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
EPTYPE[2:0]: Endpoint Type Read/Write Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 5 ISO_IN Isochronous IN 2 BULK_OUT Bulk OUT 6 BULK_IN Bulk IN 3 INT_OUT Interrupt OUT 7 INT_IN Interrupt IN DTGLE: Data Toggle Read-only 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
40.7.12 UDP FIFO Data Register Name: UDP_FDRx [x = 0..7] Address: 0x40034050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host).
40.7.13 UDP Transceiver Control Register Name: UDP_TXVC Address: 0x40034074 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
41. Analog Comparator Controller (ACC) 41.1 Description The Analog Comparator Controller (ACC) configures the analog comparator and generates an interrupt depending on user settings. The analog comparator embeds two 8-to-1 multiplexers that generate two internal inputs. These inputs are compared, resulting in a compare output. The hysteresis level, edge detection and polarity are configurable. The ACC also generates a compare event which can be used by the Pulse Width Modulator (PWM).
41.4 Pin Name List Table 41-1. 41.5 ACC Pin List Pin Name Description Type AD0..AD7 Analog inputs Input TS On-chip temperature sensor Input ADVREF ADC voltage reference Input DAC0, DAC1 On-chip DAC outputs Input FAULT Drives internal fault input of PWM Output Product Dependencies 41.5.1 I/O Lines The analog input pins (AD0-AD7 and DAC0-1) are multiplexed with digital functions (PIO) on the IO line.
41.6 Functional Description 41.6.1 Description The Analog Comparator Controller (ACC) controls the analog comparator settings and performs post-processing of the analog comparator output. When the analog comparator settings are modified, the output of the analog cell may be invalid. The ACC masks the output for the invalid period. A comparison flag is triggered by an event on the output of the analog comparator and an interrupt is generated.
41.7 Analog Comparator Controller (ACC) User Interface Table 41-3.
41.7.1 ACC Control Register Name: ACC_CR Address: 0x40040000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the module.
41.7.2 ACC Mode Register Name: ACC_MR Address: 0x40040004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 FE 13 SELFS 12 INV 11 – 10 9 8 ACEN 7 – 6 5 SELPLUS 4 3 – 2 1 SELMINUS 0 EDGETYP This register can only be written if the WPEN bit is cleared in the ACC Write Protection Mode Register. • SELMINUS: Selection for Minus Comparator Input 0..
• SELPLUS: Selection For Plus Comparator Input 0..7: Selects the input to apply on analog comparator SELPLUS comparison input. Value Name Description 0 AD0 Select AD0 1 AD1 Select AD1 2 AD2 Select AD2 3 AD3 Select AD3 4 AD4 Select AD4 5 AD5 Select AD5 6 AD6 Select AD6 7 AD7 Select AD7 • ACEN: Analog Comparator Enable 0 (DIS): Analog comparator disabled. 1 (EN): Analog comparator enabled.
23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CE • CE: Comparison Edge 0: No effect. 1: Enables the interrupt when the selected edge (defined by EDGETYP) occurs. 41.7.
1: The interrupt is enabled. 41.7.6 ACC Interrupt Status Register Name: ACC_ISR Address: 0x40040030 Access: Read-only 31 MASK 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 SCO 0 CE • CE: Comparison Edge 0: No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR.
– – – – – – – – 7 – 6 – 5 – 4 – 3 – 2 1 0 ISEL HYST This register can only be written if the WPEN bit is cleared in ACC Write Protection Mode Register. • ISEL: Current Selection Refer to the section on ACC electrical characteristics in the datasheet. 0 (LOPW): Low-power option. 1 (HISP): High-speed option. • HYST: Hysteresis Selection 0 to 3: Refer to the section on ACC electrical characteristics in the datasheet. 41.7.
41.7.9 ACC Write Protection Status Register Name: ACC_WPSR Address: 0x400400E8 Access: Read-only Reset: See Table 41-3 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of ACC_WPSR.
42. Analog-to-Digital Converter (ADC) 42.1 Description The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to Figure 42-1, "Analog-to-Digital Converter Block Diagram". It also integrates a 16-to-1 analog multiplexer, making possible the analogto-digital conversions of 16 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF.
42.
42.3 Block Diagram Figure 42-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC 12-bit Controller Trigger Selection ADTRG Control Logic ADC cell ADC Interrupt Interrupt Controller AHB PDC ADVREF AD0 Analog Inputs Peripheral Bridge PIO AD1 ADn IN+ IN- OFFSET S/H PGA Cyclic Pipeline 12-bit Analog-to-Digital Converter User Interface APB CHx GND Note: DMA is sometimes referenced as PDC (Peripheral DMA Controller).
42.4 Signal Description Table 42-1. ADC Pin Description Pin Name Description ADVREF Reference voltage (1) AD0–AD15 Analog input channels ADTRG External trigger Note: 1. AD15 is not an actual pin but is internally connected to a temperature sensor.
42.5 Product Dependencies 42.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 42.5.
Table 42-3. I/O Lines ADC AD11 PC15 X1 ADC AD12 PC12 X1 ADC AD13 PC29 X1 ADC AD14 PC30 X1 42.5.6 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be unconnected. 42.5.7 PWM Event Line PWM Event Lines may or may not be used as hardware triggers depending on user requirements. 42.5.8 Fault Output The ADC Controller has the FAULT output connected to the FAULT input of PWM.
Figure 42-2. Sequence of ADC conversions when Tracking time > Conversion time ADCClock Trigger event (Hard or Soft) ADC_ON Commands from controller to analog cell ADC_Start ADC_SEL CH0 CH1 CH2 LCDR CH0 CH1 DRDY Start Up Transfer Period Time (and tracking of CH0) Conversion of CH0 Transfer Period Conversion of CH1 Tracking of CH1 Figure 42-3.
42.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 42.6.3 Conversion Resolution The ADC supports 12-bit resolutions. 42.6.4 Conversion Results When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR).
Figure 42-5.
42.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the ADC Mode Register (ADC_MR).
numbers can be repeated several times. Only enabled sequence fields are converted, consequently to program a 15conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2. If all ADC channels (i.e., 16) are used on an application board, there is no restriction of usage of the user sequence.
Table 42-4. Input Pins and Channel Number in Single Ended Mode (Continued) Input Pins Channel Number AD7 CH7 AD8 CH8 AD9 CH9 AD10 CH10 AD11 CH11 AD12 CH12 AD13 CH13 AD14 CH14 AD15 CH15 Table 42-5. Input Pins and Channel Number In Differential Mode Input Pins Channel Number AD0–AD1 CH0 AD2–AD3 CH2 AD4–AD5 CH4 AD6–AD7 CH6 AD8–AD9 CH8 AD10–AD11 CH10 AD12–AD13 CH12 AD14–AD15 CH14 42.6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Channel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode. Table 42-7. Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G) OFFSET Bit OFFSET (DIFF = 0) 0 0 1 (G-1)Vrefin/2 OFFSET (DIFF = 1) 0 Figure 42-7.
42.6.10 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register (ADC_MR). A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time has to be programmed through the TRACKTIM field in the ADC_MR.
PWM fault input. This fault line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC Controller, the PWM outputs are immediately placed in a safe state (pure combinational path). Note that the ADC fault output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD) within the PWM configuration must be FMOD = 1. 42.6.
42.7 Analog-to-Digital Converter (ADC) User Interface Table 42-8.
42.7.1 ADC Control Register Name: ADC_CR Address: 0x40038000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 AUTOCAL 2 – 1 START 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the ADC simulating a hardware reset. • START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. • AUTOCAL: Automatic Calibration of ADC 0: No effect.
42.7.2 ADC Mode Register Name: ADC_MR Address: 0x40038004 Access: Read/Write 31 USEQ 30 – 29 23 ANACH 22 – 21 15 14 13 28 27 26 TRANSFER 25 24 17 16 TRACKTIM 20 19 18 SETTLING STARTUP 12 11 10 9 8 3 2 TRGSEL 1 0 TRGEN PRESCAL 7 FREERUN 6 FWUP 5 SLEEP 4 – This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. • TRGEN: Trigger Enable Value Name Description 0 DIS Hardware triggers are disabled.
• FWUP: Fast Wake Up Value Name Description 0 OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions 1 ON If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF • FREERUN: Free Run Mode Value Name Description 0 OFF Normal Mode 1 ON Free Run Mode: Never wait for any trigger. • PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) × 2 ).
• ANACH: Analog Change Value Name Description 0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) × ADCClock periods • TRANSFER: Transfer Period This field must be programmed with value 2.
42.7.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0x40038008 Access: Read/Write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” .
42.7.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0x4003800C Access: Read/Write 31 30 29 28 27 26 – 23 22 21 20 19 18 USCH14 15 14 13 6 24 17 16 9 8 1 0 USCH13 12 11 10 USCH12 7 25 USCH15 USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” .
42.7.5 ADC Channel Enable Register Name: ADC_CHER Address: 0x40038010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” . • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel.
42.7.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0x40038014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” . • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
42.7.7 ADC Channel Status Register Name: ADC_CHSR Address: 0x40038018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled.
42.7.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0x40038020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
42.7.9 ADC Interrupt Enable Register Name: ADC_IER Address: 0x40038024 Access: Write-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
42.7.10 ADC Interrupt Disable Register Name: ADC_IDR Address: 0x40038028 Access: Write-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
42.7.11 ADC Interrupt Mask Register Name: ADC_IMR Address: 0x4003802C Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled.
42.7.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0x40038030 Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0: The corresponding analog channel is disabled, or the conversion is not finished.
42.7.13 ADC Overrun Status Register Name: ADC_OVER Address: 0x4003803C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OVRE15 14 OVRE14 13 OVRE13 12 OVRE12 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of ADC_OVER.
42.7.14 ADC Extended Mode Register Name: ADC_EMR Address: 0x40038040 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 CMPALL 8 – 7 6 5 4 3 – 2 – 1 0 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” .
42.7.15 ADC Compare Window Register Name: ADC_CWR Address: 0x40038044 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” . • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR.
42.7.16 ADC Channel Gain Register Name: ADC_CGR Address: 0x40038048 Access: Read/Write 31 30 29 GAIN15 23 22 21 GAIN11 15 27 14 20 13 19 6 12 5 25 18 11 17 4 10 3 16 GAIN8 9 GAIN5 GAIN2 24 GAIN12 GAIN9 GAIN6 GAIN3 26 GAIN13 GAIN10 GAIN7 7 28 GAIN14 8 GAIN4 2 1 GAIN1 0 GAIN0 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” . • GAINx: Gain for Channel x Gain applied on input of analog-to-digital converter.
42.7.17 ADC Channel Offset Register Name: ADC_COR Address: 0x4003804C Access: Read/Write 31 DIFF15 30 DIFF14 29 DIFF13 28 DIFF12 27 DIFF11 26 DIFF10 25 DIFF9 24 DIFF8 23 DIFF7 22 DIFF6 21 DIFF5 20 DIFF4 19 DIFF3 18 DIFF2 17 DIFF1 16 DIFF0 15 OFF15 14 OFF14 13 OFF13 12 OFF12 11 OFF11 10 OFF10 9 OFF9 8 OFF8 7 OFF7 6 OFF6 5 OFF5 4 OFF4 3 OFF3 2 OFF2 1 OFF1 0 OFF0 This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” .
42.7.18 ADC Channel Data Register Name: ADC_CDRx [x=0..15] Address: 0x40038050 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. ADC_CDRx is only loaded if the corresponding analog channel is enabled.
42.7.19 ADC Analog Control Register Name: ADC_ACR Address: 0x40038094 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 – 6 – 5 – 4 TSON 3 – 2 – 1 – 8 IBCTL 0 – This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register” . • TSON: Temperature Sensor On 0: Temperature sensor is off. 1: Temperature sensor is on.
42.7.20 ADC Write Protection Mode Register Name: ADC_WPMR Address: 0x400380E4 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). 1: Enables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). See Section 42.6.
42.7.21 ADC Write Protection Status Register Name: ADC_WPSR Address: 0x400380E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the ADC_WPSR. 1: A write protection violation has occurred since the last read of the ADC_WPSR.
43. Digital-to-Analog Converter Controller (DACC) 43.1 Description The Digital-to-Analog Converter Controller (DACC) provides up to 2 analog outputs, making it possible for the digital-to-analog conversion to drive up to 2 independent analog lines. The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels. External triggers or free-running mode are configurable. The DACC integrates a sleep mode and connects with a PDC channel.
43.3 Block Diagram Figure 43-1. Digital-to-Analog Converter Controller Block Diagram DAC Controller Trigger Selection DATRG Control Logic DAC Clock Interrupt Controller MCK Analog Cell DAC Core PDC 43.4 Sample & Hold Sample & Hold AHB DAC0 DAC1 User Interface Peripheral Bridge APB Signal Description Table 43-1.
43.5 Product Dependencies 43.5.1 Power Management The user must first enable the DAC Controller Clock in the Power Management Controller (PMC) before using the DACC. The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is automatically deactivated when no channels are enabled. For power-saving options, see Section 43.6.6 ”Sleep Mode”. 43.5.
43.6 Functional Description 43.6.1 Digital-to-Analog Conversion The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is named DACC clock. Once a conversion starts, the DACC takes 25 clock periods to provide the analog result on the selected analog output. 43.6.2 Conversion Results When a conversion is completed, the resulting analog value is available at the selected DACC channel output and the EOC bit in the DACC Interrupt Status Register (DACC_ISR) is set.
43.6.6 Sleep Mode The DACC sleep mode maximizes power saving by automatically deactivating the DACC when it is not being used for conversions. When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the selected channel. When all conversion requests are complete, the DACC is deactivated until the next request for conversion.
Figure 43-2. Conversion Sequence MCK Select Channel 1 Select Channel 0 Write USER_SEL field Selected Channel None Channel 0 Channel 1 CDR FIFO not full TXRDY Data 0 Data 1 Data 2 Write DACC_CDR DAC Channel 0 Output Data 0 Data 1 DAC Channel 1 Output Data 2 EOC Read DACC_ISR 43.6.
43.7 Digital-to-Analog Converter (DACC) User Interface Table 43-3.
43.7.1 DACC Control Register Name: DACC_CR Address: 0x4003C000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the DACC, simulating a hardware reset.
43.7.2 DACC Mode Register Name: DACC_MR Address: 0x4003C004 Access: Read/Write 31 – 30 – 29 28 23 – 22 – 21 MAXS 20 TAG 15 14 13 12 27 26 25 24 19 – 18 – 17 11 10 9 8 3 2 TRGSEL 1 0 TRGEN STARTUP 16 USER_SEL REFRESH 7 – 6 FASTWKUP 5 SLEEP 4 WORD This register can only be written if the WPEN bit is cleared in DACC Write Protection Mode Register. • TRGEN: Trigger Enable Value Name Description 0 DIS External trigger mode disabled. DACC in free-running mode.
• SLEEP: Sleep Mode Value Name Description 0 DISABLED Normal mode: the DAC core and reference voltage circuitry are kept ON between conversions. 1 ENABLED Sleep mode: the DAC core and/or reference voltage circuitry are OFF between conversions. After reset, the DAC is in normal mode. The voltage reference and the DAC core are off. For the first conversion, a start-up time must be defined in the STARTUP field. Note that in this mode, start-up time is only required once, at startup.
• STARTUP: Startup Time Selection Value Name Description 0 0 0 periods of DACClock 1 8 8 periods of DACClock 2 16 16 periods of DACClock 3 24 24 periods of DACClock 4 64 64 periods of DACClock 5 80 80 periods of DACClock 6 96 96 periods of DACClock 7 112 112 periods of DACClock 8 512 512 periods of DACClock 9 576 576 periods of DACClock 10 640 640 periods of DACClock 11 704 704 periods of DACClock 12 768 768 periods of DACClock 13 832 832 periods of DACClock 14
Value Name Description 36 2304 2304 periods of DACClock 37 2368 2368 periods of DACClock 38 2432 2432 periods of DACClock 39 2496 2496 periods of DACClock 40 2560 2560 periods of DACClock 41 2624 2624 periods of DACClock 42 2688 2688 periods of DACClock 43 2752 2752 periods of DACClock 44 2816 2816 periods of DACClock 45 2880 2880 periods of DACClock 46 2944 2944 periods of DACClock 47 3008 3008 periods of DACClock 48 3072 3072 periods of DACClock 49 3136 3136 per
43.7.3 DACC Channel Enable Register Name: DACC_CHER Address: 0x4003C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protection Mode Register. • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel.
43.7.4 DACC Channel Disable Register Name: DACC_CHDR Address: 0x4003C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protection Mode Register. • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
43.7.5 DACC Channel Status Register Name: DACC_CHSR Address: 0x4003C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CH1 0 CH0 • CHx: Channel x Status 0: Corresponding channel is disabled. 1: Corresponding channel is enabled.
43.7.6 DACC Conversion Data Register Name: DACC_CDR Address: 0x4003C020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert When the WORD bit in DACC_MR is cleared, only DATA[15:0] is used; else DATA[31:0] is used to write two data to be converted.
43.7.
43.7.8 DACC Interrupt Disable Register Name: DACC_IDR Address: 0x4003C028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt • TXRDY: Transmit Ready Interrupt Disable.
43.7.9 DACC Interrupt Mask Register Name: DACC_IMR Address: 0x4003C02C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY The following configuration values are valid for all listed bit names of this register: 0: Corresponding interrupt is not enabled. 1: Corresponding interrupt is enabled.
43.7.10 DACC Interrupt Status Register Name: DACC_ISR Address: 0x4003C030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Flag 0: DACC is not ready to accept new conversion requests. 1: DACC is ready to accept new conversion requests.
43.7.11 DACC Analog Current Register Name: DACC_ACR Address: 0x4003C094 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 IBCTLDACCORE 7 – 6 – 5 – 4 – 3 2 1 IBCTLCH1 0 IBCTLCH0 This register can only be written if the WPEN bit is cleared in DACC Write Protection Mode Register. • IBCTLCHx: Analog Output Current Control Used to modify the slew rate of the analog output.
43.7.12 DACC Write Protection Mode Register Name: DACC_WPMR Address: 0x4003C0E4 Access: Read/Write Reset: See Table 43-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII). See Section 43.6.
43.7.13 DACC Write Protection Status Register Name: DACC_WPSR Address: 0x4003C0E8 Access: Read-only Reset: See Table 43-3 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the DACC_WPSR.
44. SAM4S Electrical Characteristics 44.1 Absolute Maximum Ratings Table 44-1. Absolute Maximum Ratings* Storage Temperature . . . . . . . . . . . . -60°C to + 150°C *NOTICE: Solder Temperature . . . . . . . . . . . . . . . . . . . . . . 260°C Voltage on Input Pins with Respect to Ground . . . . . -0.3V to + VDDIO+0.4V Maximum Operating Voltage (VDDCORE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
44.3 DC Characteristics The following characteristics are applicable to the operating temperature range: T= -40°C to 105°C, unless otherwise specified. Table 44-3.
Table 44-3. DC Characteristics (Continued) Symbol Parameter IIH Input High RPULLUP Pull-up Resistor RPULLDO Pull-down Resistor WN RODT On-die Series Termination Resistor Conditions Min Typ Max Pull-down OFF -1 — 1 Pull-down ON 10 — 50 70 100 130 kΩ 70 100 130 kΩ PA0–PA31, PB0–PB14, PC0–PC31 NRST PA0–PA31, PB0–PB14, PC0–PC31 NRST PA4–PA31, PB0–PB9, PB12–PB14, PC0–PC31 PA0–PA3 — 36 Units µA Ω 18 Random 144-bit Read @ 25°C : Maximum read frequency at VDDCORE = 1.
Table 44-4. 1.2V Voltage Regulator Characteristics Symbol Parameter Conditions Min Typ Max Units VVDDIN DC Input Voltage Range (4) (5) 1.6 3.3 3.6 V VVDDOUT DC Output Voltage — V VACCURACY Output Voltage Accuracy ILoad = 0.8 mA to 80 mA(after trimming) 3 % ILOAD Maximum DC Output Current VVDDIN > 1.8V Normal Mode Standby Mode VVDDIN ≤ 1.8V — 1.2 0 -3 — — 80 40 mA ILOAD-START Maximum Peak Current during Startup See Note(3).
Table 44-5. Core Power Supply Brownout Detector Characteristics Symbol Parameter VTH- Supply Falling Threshold(1) VHYST VTH+ IDDON Min Typ Max Units 0.98 1.0 1.04 V Hysteresis — — 110 mV Supply Rising Threshold 0.8 1.0 1.
Table 44-7. Digital Code Threshold Selection Threshold Min (V) Threshold Typ (V) Threshold Max (V) 0000 1.56 1.6 1.64 0001 1.68 1.72 1.76 0010 1.79 1.84 1.89 0011 1.91 1.96 2.01 0100 2.03 2.08 2.13 0101 2.15 2.2 2.23 0110 2.26 2.32 2.38 0111 2.38 2.44 2.50 1000 2.50 2.56 2.62 1001 2.61 2.68 2.75 1010 2.73 2.8 2.87 1011 2.85 2.92 2.99 1100 2.96 3.04 3.12 1101 3.08 3.16 3.24 1110 3.20 3.28 3.36 1111 3.32 3.4 3.49 Figure 44-2.
Table 44-8. Zero-Power-on Reset Characteristics Symbol Parameter Conditions Min Typ Max Units Vth+ Threshold Voltage Rising At startup 1.45 1.53 1.59 V Vth- Threshold Voltage Falling 1.35 1.45 1.55 V tRES Reset Time-out Period 100 340 580 µs Figure 44-3.
44.4 Power Consumption Power consumption of the device according to the different Low Power mode capabilities (backup, wait, sleep) and active mode. Power consumption on power supply in different modes: backup, wait, sleep and active. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. All power consumption values are based on characterization.
Table 44-9. Typical Power Consumption for Backup Mode (SAM4S4/S2 rev A) Backup Total Consumption @25°C @85°C @105°C Conditions (AMP1) Configuration A (AMP1) Configuration B (AMP1) Configuration A (AMP1) Configuration A VDDIO = 3.6V 1.9 1.8 6.8 14.6 VDDIO = 3.3V 1.7 1.6 6.2 13.4 VDDIO = 3.0V 1.5 1.4 5.7 12.5 VDDIO = 2.5V 1.3 1.2 5.1 11.3 VDDIO = 1.8V 0.9 0.8 4.4 9.9 Table 44-10.
44.4.2 Sleep and Wait Mode Current Consumption The wait mode and sleep mode configuration and measurements are defined below. Figure 44-5. Measurement Setup for Sleep Mode AMP2 3.3V VDDIO VDDIN Voltage Regulator VDDOUT AMP1 VDDCORE VDDPLL 44.4.2.1 Sleep Mode Core clock off VDDIO=VDDIN=3.
Figure 44-6. SAM4S4/2 Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 44-14) Sleep Mode SAM4S4/S2 8.000 6.000 ID DCORE 4.000 2.000 0.
Table 44-12. SAM4S4/S2 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA Sleep Mode Consumption Typical Value @25°C Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 120 5.1 6.9 mA 100 4.3 5.8 mA 84 3.7 5.0 mA 64 2.8 3.9 mA 32 1.5 2.2 mA 24 1.2 1.8 mA Table 44-13.
Figure 44-7. SAM4S16/S8 Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 44-14) Sleep Mode SAM4S16/S8 12.000 10.000 8.000 ID DCORE 6.000 4.000 2.000 0.000 0 Table 44-14. 10 20 30 40 50 60 MHz 70 80 90 100 110 120 SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA Sleep Mode Consumption Typical Value @25°C Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 120 8.1 9.
Table 44-15. SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with Fast RC Sleep Mode Consumption Typical Value @25°C VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit Core Clock/MCK (MHz) 12 1.1 1.5 mA 8 0.7 1.2 mA 4 0.4 0.7 mA 2 0.3 0.7 mA 1 0.2 0.5 mA 0.5 0.2 0.
Figure 44-8. SAM4SD32/SD16/SA16 Typical Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from Table 44-16) Sleep Mode SAM4SD32/SD16/SA16 9.00 8.00 7.00 6.00 5.00 IDDCORE 4.00 3.00 2.00 1.00 0.00 0 20 40 60 80 100 120 140 MHz Table 44-16.
Table 44-17. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with FAST RC Sleep Mode Consumption 44.4.2.2 Typical Value @25°C Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) Total Consumption (AMP2) Unit 12 1.1 1.8 mA 8 0.8 1.2 mA 4 0.4 0.7 mA 2 0.3 0.7 mA 1 0.2 0.5 mA 0.5 0.2 0.5 mA Wait Mode Figure 44-9. Measurement Setup for Wait Mode AMP2 3.
Table 44-18. SAM4S4/S2 Typical Current Consumption in Wait Mode Wait Mode Consumption Conditions @25°C @85°C @105°C VDDOUT Consumption (AMP1) Total Consumption (AMP2) Total Consumption (AMP2) Total Consumption (AMP2 Unit 14.9 28.4 211 436 µA 14.9 24.1 205 432 µA @85°C @105°C See Figure 44-9 on page 1116 There is no activity on the I/Os of the device. With the Flash in standby mode See Figure 44-9 on page 1116 There is no activity on the I/Os of the device.
44.4.3 Active Mode Power Consumption The active mode configuration and measurements are defined as follows: VDDIO = VDDIN = 3.3V VDDCORE = 1.2V (internal voltage regulator used) TA = 25°C Application running from Flash memory with128-bit access mode All peripheral clocks are deactivated. Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator. Current measurement on AMP1 (VDDCORE) and total current on AMP2 Figure 44-10.
44.4.3.1 SAM4S4/2 Active Power Consumption Table 44-21. SAM4S4/2 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM CoreMark Core Clock (MHz) 44.4.3.2 128-bit Flash access (1) 64-bit Flash access(1) SRAM AMP1 AMP2 AMP1 AMP2 AMP2 120 17.7 21.2 12.8 16.4 16.2 100 16.1 19.4 11.6 14.8 13.5 84 13.6 16.8 9.9 13.1 12.0 64 11.6 14.6 8.5 10.9 9.0 32 7.3 9.8 5.8 8.0 5.2 24 6.0 8.3 5.2 7.4 3.9 12 3.6 5.2 2.7 4.1 2.2 8 2.4 4.6 2.
Figure 44-11.
44.4.3.3 SAM4SD32/SD16/SA16 Active Power Consumption Table 44-23. SAM4SD32/SA16/SD16 Active Power Consumption with VDDCORE @ 1.2V running from Flash Memory (IDDCORE- AMP1) or SRAM CoreMark Cache Enable (CE) Cache Disable (CD) Core Clock (MHz) 128-bit Flash access(1) 64-bit Flash access(1) 128-bit Flash access(1) 64-bit Flash access(1) SRAM 120 20.7 20.7 24.8 18.1 19.9 100 17.5 17.4 21.6 16.5 16.8 84 14.7 14.7 18.3 13.9 14.2 64 11.3 11.3 14.4 11.5 10.9 48 8.5 8.5 11.
44.4.4 Peripheral Power Consumption in Active Mode Note: 1.
44.5 Oscillator Characteristics 44.5.1 32 kHz RC Oscillator Characteristics Table 44-24. Symbol 32 kHz RC Oscillator Characteristics Parameter Conditions Min Typ Max Unit RC Oscillator Frequency 20 32 44 kHz Frequency Supply Dependency -3 3 %/V Frequency Temperature Dependency Over temperature range (-40°C/ +105°C) versus 25°C -7 — 7 % Duty Duty Cycle 45 50 55 % tON Startup Time — — 100 µs — 540 860 nA Typ Max Unit 12 MHz % After startup time IDDON Temp.
44.5.3 32.768 kHz Crystal Oscillator Characteristics Table 44-26. 32.768 kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min freq Operating Frequency Normal mode with crystal Duty Cycle 40 Rs < 50 KΩ IDD_ON Rs < 100 KΩ Ccrystal = 12.5 pF (1) Ccrystal = 6 pF Rs < 50 KΩ Ccrystal = 12.5 pF Max Unit 32.768 kHz 60 % 900 — — 300 1200 ms 500 Ccrystal = 6 pF Current Consumption 50 Ccrystal = 12.5 pF Ccrystal = 6 pF Startup Time Typ Rs < 100 KΩ Ccrystal = 12.
44.5.5 3 to 20 MHz Crystal Oscillator Characteristics Table 44-28. 3 to 20 MHz Crystal Oscillator Characteristics Symbol Parameter Conditions freq Operating Frequency Normal mode with crystal Duty Cycle tON Typ Max Unit 3 16 20 MHz 40 50 60 % 3 MHz, CSHUNT = 3 pF 14.
44.5.6 3 to 20 MHz Crystal Characteristics Table 44-29. Symbol ESR Crystal Characteristics Parameter Conditions Equivalent Series Resistor (Rs) Min Typ Max Fundamental @ 3 MHz 200 Fundamental @ 8 MHz 100 — Fundamental @ 12 MHz Unit Ω 80 — Fundamental @ 16 MHz 80 Fundamental @ 20 MHz 50 CM Motional Capacitance — — 8 fF CSHUNT Shunt Capacitance — — 7 pF 44.5.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode Table 44-30.
44.5.8 Crystal Oscillator Design Considerations Information 44.5.8.1 Choosing a Crystal When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3–20 MHz Oscillator, several parameters must be taken into account. Important parameters of crystal and SAM4S specifications are as follows: Load Capacitance Drive Level Crystal ESR ≤ Oscillator ESR Max. Having a crystal with ESR value higher than the oscillator may cause the oscillator to not start. Shunt Capacitance 44.5.8.
44.6 PLLA, PLLB Characteristics Table 44-31. Supply Voltage Phase Lock Loop Characteristics Symbol Parameter VDDPLL Supply Voltage Range Table 44-32. Parameter fIN fOUT Typ Max Unit 1.08 1.2 1.32 V Min Typ Max Unit Input Frequency 3 — 32 MHz Output Frequency 80 — 240 MHz Active mode @ 80 MHz @1.2V 0.94 1.2 Active mode @ 96 MHz @1.2V 1.2 1.5 2.1 2.5 3.34 4 60 150 Current Consumption Conditions Active mode @ 160 MHz @1.2V — Active mode @240 MHz @1.
44.7 USB Transceiver Characteristics 44.7.1 Typical Connection For details on a typical connection, refer to the section on the USB Device Port. 44.7.2 Electrical Parameters Table 44-33. Symbol Electrical Parameters Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level — — 0.8 V VIH High Level 2.0 — — V VDI Differential Input Sensitivity 0.2 — — V VCM Differential Input Common Mode Range 0.8 — 2.
44.7.3 Switching Characteristics Table 44-34. In Full Speed Symbol Parameter Conditions Min Typ Max Unit tFR Transition Rise Time CLOAD = 50 pF 4 — 20 ns tFE Transition Fall Time CLOAD = 50 pF 4 — 20 ns tFRFM Rise/Fall Time Matching 90 — 111.11 % Figure 44-13.
44.8 12-bit ADC Characteristics Electrical data are in accordance with the following standard conditions unless otherwise specified: Operating temperature range from -40°C to + 105°C Min and max data are defined as three times the standard deviation of the manufacturing process 44.8.1 ADC Power Supply Table 44-35. Analog Power Supply Characteristics Symbol Parameter VVDDIN Supply Voltage Range IVDDIN Analog Current Consumption Conditions Min Typ Max Full operational 2.4 — 3.
44.8.2 External Reference Voltage VADVREF is an external reference voltage applied on the pin ADVREF. The quality of the reference voltage VADVREF is critical to the performance of the ADC. A DC variation of the reference voltage VADVREF is converted to a gain error by the ADC. The noise generated by VADVREF is converted by the ADC to count noise. Table 44-37.
44.8.4 ADC Transfer Function The first operation of the ADC is a sampling function relative to a common mode voltage. The common mode voltage (VCM) is equal to VADVREF/2 when the bits OFFx = 1, in Differential and in Single-ended mode. When the bits OFFx = 0, sampling is done versus VADVREF/4 for gain = 2, and VADVREF/8 for gain = 4, in Single-ended mode only. The code in ADC_CDRx is a 12-bit positive integer. 44.8.4.
44.8.4.3 Example of LSB Computation The LSB is relative to the analog scale VADVREF. The term LSB expresses the quantization step in volts, also used for one ADC code variation. Single-ended (SE) (ex: VADVREF=3.0V) Gain = 1, LSB = (3.0V / 4096) = 732 µV Gain = 2, LSB = (1.5V / 4096) = 366 µV Gain = 4, LSB = (750 mV / 4096) = 183 µV Differential (DIFF) (ex: VADVREF=3.0V) Gain = 0.5, LSB = (6.0V / 4096) = 1465 µV Gain = 1, LSB = (3.0V / 4096) = 732 µV Gain = 2, LSB = (1.
Differential Mode In differential mode, the offset is defined when the differential input voltage is zero. Figure 44-14.
Single-ended Mode Figure 44-15 illustrates the ADC output code relative to an input voltage VIN between 0V (Ground) and VADVREF. The ADC is configured in Single-ended mode by connecting internally the negative differential input to VADVREF/2. As the ADC continues to work internally in Differential mode, the offset is measured at VADVREF/2. Figure 44-15.
44.8.5.2 ADC Electrical Performances Single-ended Static Performances Table 44-47. Single-ended Static Electrical Characteristics Symbol Parameter INL DNL Conditions Min Typ Max Unit ADC Integral Non-linearity -2 +/-1 2 LSB ADC Differential Non-linearity -1 -+/-0.5 1 LSB Single-ended Dynamic Performances Table 44-48.
Low Voltage Supply The ADC performs in 10-bit mode or in 12-bit mode. Working at low voltage (VDDIN or/and VADVREF) between 2 and 2.4V is subject to the following restrictions: 44.8.5.3 The field IBCTL must be 00 to reduce the biasing of the ADC under low voltage. See Section 44.8.1.1 “ADC Bias Current”. In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz). In 12-bit mode, the ADC clock should not exceed 2 MHz (max signal bandwidth is 100 kHz).
Table 44-52. ZIN Input Impedance fS (MHz) 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 8 16 32 64 4 8 16 32 2 4 8 16 CIN = 2 pF ZIN (MΩ) 0.5 1 2 4 CIN = 4 pF ZIN (MΩ) 0.25 0.5 1 2 CIN = 8 pF ZIN (MΩ) 0.125 0.25 0.5 1 Track and Hold Time versus Source Output Impedance Figure 44-17 shows a simplified acquisition path. Figure 44-17.
44.9 12-bit DAC Characteristics Table 44-53. Analog Power Supply Characteristics Symbol Parameter VVDDIN Analog Supply Conditions Min Typ Max Units 2.4 3.0 3.6 V 3 µA Sleep Mode( Clock OFF) Current Consumption IVDDIN Fast Wake Up (Standby Mode, clock ON) Normal Mode with 1 output ON (IBCTLDACCORE = 01, IBCTLCHx =10) — Normal Mode with 2 outputs ON (IBCTLDACCORE =01, IBCTLCHx =10) Table 44-54. 2 3 mA 4.3 5.6 mA 5 6.
Table 44-56. Dynamic Performance Characteristics Parameter Conditions 2.4V < VVDDIN < 2.7V Min Typ Max 50 62 70 Signal to Noise Ratio - SNR dB 2.7V < VVDDIN < 3.6V 62 70 74 2.4V < VVDDIN < 2.7V -78 -64 -60 Total Harmonic Distortion - THD dB 2.7V < VVDDIN < 3.6V -80 -74 -72 2.4V < VVDDIN < 2.7V 50 60 70 Signal to Noise and Distortion - SINAD dB 2.7V < VVDDIN < 3.6V 62 68 73 2.4V < VVDDIN < 2.7V 8 10 12 2.7V < VVDDIN < 3.
44.10 Analog Comparator Characteristics Table 44-58. Analog Comparator Characteristics Parameter Conditions Min Typ Max Units Voltage Range Analog comparator is supplied by VDDIN 1.62 3.3 3.6 V Input Voltage Range GND + 0.2 — VDDIN - 0.
44.12 AC Characteristics 44.12.1 Master Clock Characteristics Table 44-60. Master Clock Waveform Parameters Symbol Parameter Conditions Min Max Units 1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.20V — 120 MHz 1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.08V — 100 MHz 44.12.
4. Pin Group 4 = PA[0–3] 5. Pin Group 5 = PB[10–11] 44.12.3 SPI Characteristics Figure 44-18. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 44-19. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 44-20.
Figure 44-21. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 44.12.3.1 Maximum SPI Frequency The following formulas give maximum SPI frequency in master read and write modes and in slave read and write modes. Master Write Mode The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 44.12.
44.12.3.2 SPI Timings Table 44-62. Symbol SPI0 SPI Timings Parameter MISO Setup Time before SPCK Rises (Master) Conditions Min Max Units (1) 3.3V domain 11.3 — ns 1.8V domain(2) 13.
44.12.5 SSC Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF Figure 44-22. SSC Transmitter, TK and TF as Output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 44-23. SSC Transmitter, TK as Input and TF as Output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 44-24.
Figure 44-25. SSC Transmitter, TK and TF as Input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD Figure 44-26. SSC Receiver RK and RF as Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 44-27.
Figure 44-28. SSC Receiver, RK and RF as Output RK (CKI=1) RK (CKI=0) SSC12 SSC11 RD SSC13 RF Figure 44-29. SSC Receiver, RK as Output and RF as Input RK (CKI=0) RK (CKI=1) SSC12 SSC11 RF/RD Table 44-63.
Table 44-63. Symbol SSC7(1) SSC Timings (Continued) Parameter Condition TK Edge to TF/TD (TK Input, TF Input) 1.8V domain (3) 3.3V domain (4) Min Max Units 4.5(+3*tCPMCK) (1)(4) (1)(4) 16.3(+3*tCPMCK) 3.8(+3*tCPMCK) (1)(4) 13.
44.12.6 SMC Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF. Timings are given assuming a capacitance load on data, control and address pads: In the following tables tCPMCK is MCK period. Timing extraction 44.12.6.1 Read Timings Table 44-64. Symbol SMC Read Signals - NRD Controlled (READ_MODE = 1) Parameter Min VDDIO Supply 1.8V (2) Max 3.
Table 44-65. Symbol SMC Read Signals - NCS Controlled (READ_MODE = 0) Parameter Min VDDIO Supply 1.8V (2) Max 3.3V (3) (2) Units 1.8V 3.3V (3) NO HOLD Settings (NCS rd Hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High 20.7 18.4 — — ns 0 0 — — ns HOLD Settings (NCS rd Hold ≠ 0) SMC10 Data Setup before NCS High SMC11 Data Hold after NCS High 16.8 14.
44.12.6.2 Write Timings Table 44-66. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V (2) Max (3) 3.3V 1.8V (2) 3.3V(3) Units HOLD or NO HOLD Settings (NWE hold ≠ 0, NWE hold = 0) SMC15 Data Out Valid before NWE High NWE pulse * tCPMCK -6.9 NWE pulse * tCPMCK - 3.3 — — ns SMC16 NWE Pulse Width NWE pulse * tCPMCK - 7.3 NWE pulse * tCPMCK - 6.3 — — ns SMC17 A0 - A22 Valid before NWE Low NWE setup * tCPMCK - 7.2 NWE setup * tCPMCK - 7.
Table 44-67. SMC Write Signals - NCS Controlled (WRITE_MODE = 0) Min Max 3.3V(3) Units — — ns NCS wr pulse * tCPMCK - 6.7 — — ns NCS wr setup * tCPMCK - 6.5 NCS wr setup * tCPMCK - 6.3 — — ns (NCS wr setup NWE setup + NCS pulse)* tCPMCK - 5.1 (NCS wr setup NWE setup + NCS pulse)* tCPMCK - 4.9 — — ns NCS High to Data Out, A0 - A25, Change NCS wr hold * tCPMCK - 10.2 NCS wr hold * tCPMCK - 8.4 — — ns NCS High to NWE Inactive (NCS wr hold NWE hold)* tCPMCK - 2.
Figure 44-31. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0 - A23 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 DATA SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 44-32.
44.12.7 USART in SPI Mode Timings Timings are given in the following domain: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF Figure 44-33.
Figure 44-35.
44.12.7.1 USART SPI TImings Table 44-68. Symbol USART SPI Timings Parameter Conditions Min Max Units MCK/6 — ns 0.5 * MCK + 0.8 0.5 * MCK + 1.0 — ns 1.5 * MCK + 0.3 1.5 * MCK + 0.1 — ns 1.5 * SPCK - 1.5 1.5 * SPCK - 2.1 — ns - 7.9 - 7.2 9.9 10.7 ns 1 * SPCK - 7.7 1 * SPCK - 11.8 — ns 4.7 4 17.3 15.2 ns 2 * MCK + 0.7 2 * MCK — ns 0 0.1 — ns 4.7 4.1 20.1 15.5 ns 2 * MCK + 0.7 2 * MCK + 0.6 — ns 0.2 0.1 — ns 2.5 * MCK + 0.5 2.5 * MCK — ns 1.5 * MCK + 0.2 1.
44.12.8 Two-wire Serial Interface Characteristics Table 44-69 describes the requirements for devices connected to the Two-wire serial bus. For timing symbols refer to Figure 4436. Table 44-69. Two-wire Serial Bus Requirements Symbol Parameter VIL Condition Min Max Units Input Low-voltage -0.3 0.3 VVDDIO V VIH Input High-voltage 0.7 x VVDDIO VCC + 0.3 V VHYS Hysteresis of Schmitt Trigger Inputs 0.150 — V VOL Output Low-voltage - 3 mA sink current 0.4 V 0.
4. The TWCK high period is defined as follows: t high = ( ( CHDIV × 2 5. tCP_MCK = MCK bus period. CKDIV ) + 4 ) × t MCK Figure 44-36.
44.12.9 Embedded Flash Characteristics The maximum operating frequency given in Table 44-70 is limited by the embedded Flash access time when the processor is fetching code out of it. Table 44-70 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the embedded Flash memory. The embedded Flash is fully tested during production test. The Flash contents are not set to a known state prior to shipment.
45. SAM4S Mechanical Characteristics Figure 45-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. Table 45-1. Device and LQFP Package Maximum Weight SAM4S Table 45-2. 800 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 45-3. mg LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
Figure 45-2. 100-ball TFBGA Package Drawing Table 45-4. TFBGA Package Reference - Soldering Information (Substrate Level) Ball Land Diameter 450 µm Soldering Mask Opening 350 µm Table 45-5. Device and 100-ball TFBGA Package Maximum Weight SAM4S Table 45-6.
Figure 45-3. 100-ball VFBGA Package Drawing Table 45-7. VFBGA Package Dimensions Symbol Package: Common Dimensions (mm) VFBGA X E 7.000 ± 0.100 Y D 7.000 ± 0.100 X eE 0.650 Y eD 0.650 Total Thickness: A 1.000 max Mold Thickness: M 0.450 ref. Substrate Thickness: S 0.210 ref. Body Size: Ball Pitch: Ball Diameter: 0.
Table 45-7. VFBGA Package Dimensions (Continued) Symbol Common Dimensions (mm) Stand Off: A1 0.160 ~ 0.260 Ball Width: b 0.270 ~ 0.370 Package Edge Tolerance: aaa 0.100 Mold Flatness: bbb 0.100 Coplanarity: ddd 0.080 Ball Offset (Package): eee 0.150 Ball Offset (Ball): fff 0.080 Ball Count: n 100 X E1 5.850 Y D1 5.850 X I 0.575 Y J 0.575 Edge Ball Center to Center: Corner Ball Center to Package Edge: Table 45-8.
Figure 45-4.
Table 45-12. 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.
Figure 45-5. 64-lead QFN Package Drawing Table 45-16. Device and QFN Package Maximum Weight (Preliminary) SAM4S Table 45-17. 280 mg QFN Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification e3 Table 45-18. QFN Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
Figure 45-6. 64-ball WLCSP Package Mechanical Drawing Table 45-19. 64-ball WLCSP Package Dimensions (in mm) Common Dimensions Symbol MIN. NOM. MAX. Total Thickness A 0.455 0.494 0.533 Stand Off A1 0.17 - 0.23 Wafer Thickness A2 0.254 +/- 0.025 D 4.424 BSC(1)/3.323 BSC(2) E 3.420 BSC(1)/3.323 BSC(2) Body Size Ball Diameter (Size) Ball/Bump Width 0.25 b 0.23 0.26 eD 0.4 eE 0.4 n 64 0.29 Ball/Bump Pitch Ball/Bump Count Notes: 1. 2. For SAM4S16. For SAM4S4.
Table 45-19. 64-ball WLCSP Package Dimensions (in mm) Common Dimensions Symbol MIN. NOM. D1 2.8 BSC E1 2.8 BSC Package Edge Tolerance aaa 0.03 Coplanarity (Whole Wafer) ccc 0.075 Ball/Bump Offset (Package) ddd 0.05 Ball/Bump Offset (Ball) eee 0.015 MAX. Edge Ball Center to Center Figure 45-7. UBM Pad Installation Table 45-20. WLCSP Package Reference - Soldering Information (Substrate Level) UBM Pad (Under Bump Metallurgy) (E) 200 µm PBO2 Opening (j) 240 µm Table 45-21.
Figure 45-8. 48-lead LQFP Package Drawing 1.0 1.0 1.0 1 2 3 1 Table 45-24. Device and 48-lead LQFP Package Maximum Weight SAM4S Table 45-25. 190 48-lead LQFP Package Characteristics Moisture Sensitivity Level Table 45-26.
Figure 45-9. 48-lead QFN Package Drawing Table 45-27. Device and 48-lead LQFP Package Maximum Weight SAM4S Table 45-28. 143 48-lead LQFP Package Characteristics Moisture Sensitivity Level Table 45-29.
45.1 Soldering Profile Table 45-30 gives the recommended soldering profile from J-STD-020C. Table 45-30. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ± 25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
46. Errata on SAM4S Devices 46.1 Errata SAM4SD32/SD16/SA16/S16/S8 Rev A Parts The errata are applicable to the devices in Table 46-1. Table 46-1. Device List for Errata Described in Section 46.
46.1.2 Flash 46.1.2.1 Flash: Read Error after a GPNVM or Lock Bit Writing The sequence below leads to a bad read value. Fail sequence is: Read Flash @ address XXX Programming Flash: Write GPNVM or Lock Bit instructions Read Flash @ address XXX Problem Fix/Workaround A dummy read at another address needs to be included in the sequence. Sequence is: Read Flash @ address XXX Programming Flash: Write GPNVM or Lock Bit instructions Read Flash @ address YYY (dummy read) Read Flash @ address XXX 46.1.
46.2 Errata SAM4S4/S2 Rev. A Parts The errata are applicable to the devices in Table 46-2. Table 46-2. Device List for Errata Described in Section 46.2 Device Name Chip ID SAM4S4C (Rev A) 0x28AB_09E0 SAM4S4B (Rev A) 0x289B_09E0 SAM4S4A (Rev A) 0x288B_09E0 SAM4S2C (Rev A) 0x28AB_07E0 SAM4S2B (Rev A) 0x289B_07E0 SAM4S2A (Rev A) 0x288B_07E0 46.2.1 Flash Controller 46.2.1.
47. Ordering Information Devices in TFBGA, VFBGA, LQFP and QFN packages can be ordered in trays or in tape and reel. Devices in a WLCSP package are available in tape and reel only. Table 47-1 provides ordering codes for tray packing. For tape and reel, append an ‘R’ to the tray ordering code; e.g. ATSAM4SD32CA-CUR. Table 47-1.
Table 47-1.
Table 47-1.
48. Revision History In the tables that follow, the most recent version of the document appears first. Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History Changes Uupdate to add SAM4S4 and SAM4S2 devices. “Description” 48-pin package option added at end of section. “Features” ”System”: Added bullet on tamper detection and anti-tampering feature “Packages” : Modified dimensions of 64-ball WLCSP package used for SAM4S16/S8. Added 48-lead package options. Section 1.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 12. “ARM Cortex-M4 Processor” Section 12.5.3 “Power Management Programming Hints”: in 2nd instruction line, replaced “WFE(void)” with “WFI(void)” to match ‘Wait For Interrupt’ and in 2nd instruction line, replaced “WFE(void)” with “WFI(void)” to match ‘Wait For Interrupt’ Section 12.9.1.2 “CPUID Base Register”: updated ‘Constant’ field description Section 12.9.1.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 16. “Real-time Clock (RTC)” Section 16. “Real-time Clock (RTC)”: updated to explain need for accurate external 32.768 kHz clock Section 16.2 “Embedded Characteristics”: added feature “Write-Protected Registers” Section 16.5.6 “Updating Time/Calendar”: reworded second paragraph for clarity Section 16.5.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 20. “Enhanced Embedded Flash Controller (EEFC)” Corrected partial programming boundary from 32-bit to 64-bit and reworked Section 20.4.3.2 “Write Commands” and all sub-sections with figures Figure 20-7 Full Page Programming to Figure 20-9 Programming Bytes in the Flash. In Section 20.4.3.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 33. “Serial Peripheral Interface (SPI)” ‘MCK’ replaced with ‘peripheral clock’ throughout. Updated Figure 33-1 ”Block Diagram”, Figure 33-3 ”SPI Transfer Format (NCPHA = 1, 8 bits per transfer)” and Figure 33-4 ”SPI Transfer Format (NCPHA = 0, 8 bits per transfer)” Modified Section 33.7.3 “Master Mode Operations”, Modified Section 33.7.5 “Register Write Protection”, Section 33.8.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 38. “High Speed MultiMedia Card Interface (HSMCI)” Changed PDCFBYTE to FBYTE in Section 9.6 “WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller” and in Section 9.8 “READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller”. Section 14. “Register Write Protection”: changed title (was “Write Protection Registers”); revised content In Section 15.
Table 48-1. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 43. “Digital-to-Analog Converter Controller (DACC)” Section 43.7.7 “DACC Interrupt Enable Register”, Section 43.7.8 “DACC Interrupt Disable Register” and Section 43.7.9 “DACC Interrupt Mask Register”: modified bit descriptions. Rework of all “refresh” related paragraphs, Section 43.7.3 “DACC Channel Enable Register” and Section 43.6.7 “DACC Timings”.
Table 48-2. SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History Change Request Ref. Doc. Rev. 11100E Comments Introduction Added WLCSP64 package in Section “Features”, Table 1-1, “Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices”, added Figure 4-6 and Table 4-5, “SAM4S16/S8 64-ball WLCSP Pinout”. 8620 Updated Section 5.5 “Low-power Modes”. Added information on WFE. 9073 Added 2nd paragraph in Section 6.1 “General Purpose I/O Lines”.
Table 48-2. SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History (Continued) Change Request Ref. Doc. Rev. 11100E Comments Ordering Information New ordering codes (105 °C, reel conditioning, WLCSP package) added in Table 47-1, “Ordering Codes for SAM4S Devices”. 8620, rfo Errata Added Section 46.1.3.1 “Watchdog Not Stopped in Wait Mode” and Section 46.1.4.1 “Unpredictable Behavior if 9075 BOD is Disabled, VDDCORE is Lost and VDDIO is Connected”.
Table 48-4. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History Change Request Ref. Doc. Rev. 11100C Comments Introduction In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-3, Figure 8386 2-4, Figure 3. and Figure 2-2. Reference to the LPM bit removed in the whole datasheet. 8392 Flash rails mentioned in Section 5.1 “Power Supplies”. 8406 Section 9. “Real Time Event Management” created.
Table 48-4. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continued) Change Request Ref. Doc. Rev. 11100C Comments CMCC Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register” and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description completed.
Table 48-4. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continued) Change Request Ref. Doc. Rev. 11100C Comments TWI NVIC and AIC changed to Interrupt Controller. Section 33.10.4.5 “PDC” removed. “This bit is only used in Master mode” removed from bitfields ENDRX, ENDTX, RXBUFF, and TXBUFE in Section 33.11.6 “TWI Status Register”. 7844 Figure 33-23 updated: SVREAD = 1 and first occurrence of RXRDY = 1. 7884 Removed “20” at the end of the 1st paragraph in Section 33.1 “Description”.
. Table 48-5. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History Change Request Ref. Doc. Rev. 11100B Comments Introduction 48 pins packages (SAM4S16A and SAM4S8A devices) removed. 8100 Write Protected Registers added in “Description” on page 1. 8213 Note related to EWP and EWPL commands added in Section 8.1.3.1 “Flash Overview” on page 36. 8225 References to WFE instructions replaced by relevant bits precise descriptions.
Table 48-5. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued) Change Request Ref. Doc. Rev. 11100B Comments RTC In Section 16.6.2 “RTC Mode Register” on page 268, formulas associated with conditions HIGHPPM = 1 and HIGHPPM = 0 have been swapped, text has been clarified. 7950 In Section 16.5.7 “RTC Accurate Clock Calibration” on page 264, paragraph describing RTC clock calibration circuitry correction updated with mention of crystal drift.
Table 48-5. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued) Change Request Ref. Doc. Rev. 11100B Comments PMC Added a note in Section 28.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 477. 7848 Max MULA/MULB value changed from 2047 to 62 in Section 28.2.16.9 “PMC Clock Generator PLLA Register” 8064 on page 480 and Section 28.2.16.10 “PMC Clock Generator PLLB Register” on page 481. Step 5 in Section 28.2.
Table 48-6. SAM4S Datasheet Rev. 11100A 28-Oct-11 Revision History Doc. Rev. 11100A Comments Change Request Ref. First issue.
Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Cortex-M4 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4 Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 19. General-Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . 338 19.1 19.2 19.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 General Purpose Backup Registers (GPBR) User Interface . . . . . . . . . . . . 339 20.
26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.2 30.3 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 31. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . 548 31.1 31.2 31.3 31.4 31.5 31.6 31.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . .
35.6 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . 734 36. Universal Synchronous Asynchronous Receiver Transceiver (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 36.1 36.2 36.3 36.4 36.5 36.6 36.7 36.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40.4 40.5 40.6 40.7 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 USB Device Port (UDP) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005 41. Analog Comparator Controller (ACC) . . . . . . . . . . . . . .
46.2 Errata SAM4S4/S2 Rev. A Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176 47. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 48. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.
