Datasheet

373
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
22. Cortex-M Cache Controller (CMCC)
22.1 Description
The Cortex-M Cache Controller (CMCC) is a four-way set associative unified cache controller. It integrates a controller, a
tag directory, data memory, metadata memory and a configuration interface.
22.2 Embedded Characteristics
 Physically addressed and physically tagged
 L1 data cache set to 2 Kbytes
 L1 cache line size set to 16 Bytes
 L1 cache integrates 32-bit bus master interface
 Unified Direct mapped cache architecture
 Unified four-way set associative cache architecture
 Write through cache operations, read allocate
 Round Robin victim selection policy
 Event Monitoring, with one programmable 32-bit counter
 Configuration registers accessible through Cortex-M Private Peripheral Bus
 Cache Interface includes cache maintenance operations registers