Datasheet

984
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
39.7.40 PWM Channel Period Update Register
Name: PWM_CPRDUPDx [x=0..3]
Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Access: Write-only
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the “PWM Write Protection Status Register” .
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform
period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CPRDUPD
15 14 13 12 11 10 9 8
CPRDUPD
76543210
CPRDUPD
X CPRDUPD×()
MCK
--------------------------------------------
CRPDUPD DIVA×()
MCK
--------------------------------------------------------
CRPDUPD DIVB×()
MCK
--------------------------------------------------------
2 X CPRDUPD××()
MCK
------------------------------------------------------
2 CPRDUPD DIVA××()
MCK
-----------------------------------------------------------------
2 CPRDUPD× DIVB×()
MCK
-----------------------------------------------------------------