Datasheet

933

SAM4S Series [DATASHEET]

11100F–ATARM–29-Jan-14

comparison is made when the counter is counting up or counting down (in left alignment mode CALG = 0, this bit is

useless).

If a fault is active on the channel 0, the comparison is disabled and cannot match (see Section 39.6.2.6 “Fault

Protection”).

The user can define the periodicity of the comparison x by the fields CTR and CPR (in PWM_CMPVx). The comparison

is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison

period counter CPRCNT (in PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the

comparison period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the counter of the

channel 0.

The comparison x configuration can be modified while the channel 0 is enabled by using the “PWM Comparison x Mode

Update Register” (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x value can be

modified while the channel 0 is enabled by using the “PWM Comparison x Value Update Register” (PWM_CMPVUPDx

registers for the comparison x).

The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x

update period. It is defined by the field CUPR in the PWM_CMPMx. The comparison unit has an update period counter

independent from the period counter to trigger this update. When the value of the comparison update period counter

CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update

period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register.

CAUTION:

to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the

The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not

masked. These interrupts can be enabled by the “PWM Interrupt Enable Register 2” and disabled by the “PWM Interrupt

Disable Register 2” . The comparison match interrupt and the comparison update interrupt are reset by reading the

“PWM Interrupt Status Register 2” .