Datasheet

843
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
37.7.2 TC Channel Mode Register: Capture Mode
Name: TC_CMRx [x=0..2] (WAVE = 0)
Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084
(1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.