Datasheet

81
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
12.5 Power Management
The Cortex-M4 processor sleep modes reduce the power consumption:
 Sleep mode stops the processor clock
 Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.
12.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore,
the software must be able to put the processor back into sleep mode after such an event. A program might have an idle
loop to put the processor back to sleep mode.
12.5.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI
instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
12.5.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register.
When the processor executes a WFE instruction, it checks this register:
 If the register is 0, the processor stops executing instructions and enters sleep mode
 If the register is 1, the processor clears the register to 0 and continues executing instructions without entering
sleep mode.
See “WFE” for more information.
12.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception handler, it
returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the
processor to run when an exception occurs.
12.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
12.5.2.1 Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt
arrives that is enabled and has a higher priority than the current exception priority, the processor wakes up but does not
execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and
FAULTMASK, see “Exception Mask Registers” .
12.5.2.2 Wakeup from WFE
The processor wakes up if:
 It detects an exception with sufficient priority to cause an exception entry
 It detects an external event signal. See “External Event Input”
 In a multiprocessor system, another processor in the system executes an SEV instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the
processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more information
about the SCR, see “System Control Register” .