Datasheet
777
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. Likewise,
the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART
SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least
6 times lower than the system clock.
36.7.8.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are selected by
setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode (master or slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the
clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four
possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter
pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure
itself each time it needs to communicate with a different slave.
Figure 36-38. SPI Transfer Format (CPHA = 1, 8 bits per transfer)
Table 36-15. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
MISO
SPI Master ->RXD
SPI Slave -> TXD