Datasheet

675
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
33.8.5 SPI Status Register
Name: SPI_SR
Address: 0x40008010
Access: Read-only
 RDRF: Receive Data Register Full
0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the shift register to SPI_RDR since the last read of
SPI_RDR.
 TDRE: Transmit Data Register Empty
0: Data has been written to SPI_TDR and not yet transferred to the shift register.
1: The last data written in the SPI_TDR has been transferred to the shift register.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
 MODF: Mode Fault Error
0: No mode fault has been detected since the last read of SPI_SR.
1: A mode fault occurred since the last read of SPI_SR.
 OVRES: Overrun Error Status
0: No overrun has been detected since the last read of SPI_SR.
1: An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the shift register since the last read of the SPI_RDR.
 ENDRX: End of RX buffer
0: The Receive Counter register has not reached 0 since the last write in SPI_RCR
(1)
or SPI_RNCR
(1)
.
1: The Receive Counter register has reached 0 since the last write in SPI_RCR
(1)
or SPI_RNCR
(1)
.
 ENDTX: End of TX buffer
0: The Transmit Counter register has not reached 0 since the last write in SPI_TCR
(1)
or SPI_TNCR
(1)
.
1: The Transmit Counter register has reached 0 since the last write in SPI_TCR
(1)
or SPI_TNCR
(1)
.
 RXBUFF: RX Buffer Full
0: SPI_RCR
(1)
or SPI_RNCR
(1)
has a value other than 0.
1: Both SPI_RCR
(1)
and SPI_RNCR
(1)
have a value of 0.
 TXBUFE: TX Buffer Empty
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––SPIENS
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF