Datasheet

672

SAM4S Series [DATASHEET]

11100F–ATARM–29-Jan-14

LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on MOSI).

 PCS: Peripheral Chip Select

This field is only used if fixed peripheral select is active (PS = 0).

If PCSDEC = 0:

PCS = xxx0 NPCS[3:0] = 1110

PCS = xx01 NPCS[3:0] = 1101

PCS = x011 NPCS[3:0] = 1011

PCS = 0111 NPCS[3:0] = 0111

PCS = 1111 forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS.

 DLYBCS: Delay Between Chip Selects

This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guarantees non-overlapping

chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is less than or equal to six, six peripheral clock periods are inserted by default.

Otherwise, the following equation determines the delay:

Delay Between Chip Selects

DLYBCS

peripheral clock

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