Datasheet

667
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
external master on the NPCS0/NSS signal. In multi-master environment, NPCS0, MOSI, MISO and SPCK pins must be
configured in open drain (through the PIO controller). When a mode fault is detected, the MODF bit in SPI_SR is set until
SPI_SR is read and the SPI is automatically disabled until it is re-enabled by writing the SPIEN bit in SPI_CR to 1.
By default, the mode fault detection is enabled. The user can disable it by setting the MODFDIS bit in SPI_MR.
33.7.4 SPI Slave Mode
When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits until NSS goes active before receiving the serial clock from an external master. When NSS falls, the clock
is validated and the data is loaded in SPI_RDR depending on the BITS field configured in SPI_CSR0. These bits are
processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in SPI_CSR0. Note that
BITS, CPOL and NCPHA of the other Chip Select registers have no effect when the SPI is programmed in Slave mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
Note: For more information on the BITS field, see also the note below the SPI_CSRx register table; Section 33.8.9
”SPI Chip Select Register” .)
When all bits are processed, the received data is transferred in SPI_RDR and the RDRF bit rises. If SPI_RDR has not
been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data
is loaded in SPI_RDR. The user must read SPI_SR to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift register. If no data has been written in
SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted
low, as the Shift register resets to 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift register and the TDRE flag rises. If new
data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin.
When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift register and the TDRE flag rises.
This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift register from SPI_TDR. If no character is ready to be transmitted, i.e. no character
has been written in SPI_TDR since the last load from SPI_TDR to the Shift register, the SPI_TDR is retransmitted. In this
case the Underrun Error Status Flag (UNDES) is set in the SPI_SR.
Figure 33-12 shows a block diagram of the SPI when operating in Slave mode.
Figure 33-12. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO