Datasheet

661
SAM4S Series [DATASHEET]
11100F–ATARM–29-Jan-14
Figure 33-7 shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
Transmission Register Empty (TXEMPTY) status flags within SPI_SR during an 8-bit data transfer in Fixed mode without
the Peripheral Data Controller involved.
Figure 33-7. Status Register Flags Behavior
Figure 33-8 shows the behavior of Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX
buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags within SPI_SR during an 8-bit
data transfer in Fixed mode with the Peripheral Data Controller involved. The PDC is programmed to transfer and receive
three data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are
managed by the PDC when using the PDC.
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty